Abstract: The invention concerns a unit for switching data transmitted by asynchronous time-division multiplexing comprising receive circuits (CRl/i) supplying cells received via input links, transmit circuits (CTl/j) transmitting retransmitted cells on output links, a buffer memory (MT) storing the received cells and delivering the cells to be retransmitted and a buffer memory addressing device (SMT) including a write address source (SAE) and a read address source (fsl/j).The switching unit further comprises a write disabling circuit (pi) conditioned by a signal (adl) derived from the content of at least one received cell or a signal (tle) derived from the absence of any received cell and supplying a disabling signal (spi) and the address source includes a disabling device (pac, pal) influenced by the disabling signal (spi) so that no memory location is then occupied in the buffer memory (MT).

Abstract: A management unit for a unit for switching data transmitted by asynchronous time-division multiplexing. It comprises input circuits (gme, gpe) adapted to receive cells present on the input bus (BE) of the switching unit and output circuits (grs, grv) adapted to supply cells on the output bus (BS) of the switching unit. The input circuits comprise a call circuit (gpe) detecting a call signal (adl) from the switching unit and commanding the writing of the cell present on the input bus (BE) into an input memory (gme). The output circuits comprise a transmit circuit (gpl) receiving an availability signal (fv) and determining the transmission of the cell that an output register (grs, grv) contains on the output bus (BS).

Abstract: The switching circuit comprises an interface to the interior which comprises two-way gates which are connected to internal interfaces of other switching circuits of said network, each of said gates comprising a l-input and n-output receive circuit and an n-input and l-output transmit circuit, one input of the transmit circuit being connected to the output of a receive circuit different for each of the n inputs, and the input of each receive circuit of a gate being connected to the output of the transmit circuit of a gate of another switching circuit of said network.