Abstract: Disclosed is a polyurethane foam and a method of preparing the same which utilizes only bio-renewable polyols and no petroleum derived polyols. The polyol is derived from a bio-renewable source and has a bio-renewable content of at least 70% by weight. The produced foams have mechanical and performance properties that are equal to or exceed those of similar polyurethane foams produced using petroleum derived polyols. The foams are preferably formed into sponges and other cleaning products for use by consumers and in industrial settings.

Abstract: The present disclosure describes a flexible polyurethane foam having suspended within its matrix particles of silicon dioxide, SiO2. The particles of silicon dioxide are interspersed within the polyurethane matrix and protrude from the surface of the foam. These particles form an abrasive surface and the produced foam finds use as a cleaning material. The foam includes the use of a pre-polymer polyol formed by the reaction of triol polyol having a molecular weight of from 700 to 8000 with a polyisocyanate and a tin catalyst. The produced foam is much more durable than commercially available melamine foams and is an effective cleaning foam.

Abstract: Disclosed is a polyurethane foam and a method of preparing the same which utilizes only bio-renewable polyols and no petroleum derived polyols. The polyol is derived from a bio-renewable source and has a bio-renewable content of at least 70% by weight. The produced foams have mechanical and performance properties that are equal to or exceed those of similar polyurethane foams produced using petroleum derived polyols. The foams are preferably formed into sponges and other cleaning products for use by consumers and in industrial settings.

Abstract: A direct and simple method to control cell size in a polyurethane foam is disclosed. Polyurethane foam is made by mixing prepolymer with foam-forming ingredients comprising isocyanate and water which react to give carbon dioxide. The reaction is driven by a catalyst and results in a foam structure with cells of a particular size. Using the addition of a pre-determined amount of mineral oil, the coalescence of neighboring cells of the foam structure may be advantageously controlled to form a cell structure with a desired average cell size.

Abstract: A direct and simple method to control cell size in a polyurethane foam is disclosed. Polyurethane foam is made by mixing prepolymer with foam-forming ingredients comprising isocyanate and water which react to give carbon dioxide. The reaction is driven by a catalyst and results in a foam structure with cells of a particular size. Using the addition of a pre-determined amount of mineral oil, the coalescence of neighboring cells of the foam structure may be advantageously controlled to form a cell structure with a desired average cell size.

Abstract: The present disclosure describes a flexible polyurethane foam having suspended within its matrix particles of silicon dioxide, SiO2. The particles of silicon dioxide are interspersed within the polyurethane matrix and protrude from the surface of the foam. These particles form an abrasive surface and the produced foam finds use as a cleaning material. The foam includes the use of a pre-polymer polyol formed by the reaction of triol polyol having a molecular weight of from 700 to 8000 with a polyisocyanate and a tin catalyst. The produced foam is much more durable than commercially available melamine foams and is an effective cleaning foam.

Abstract: A method of optimizing clock network capacitance of an integrated circuit (IC) including identifying any crossover points between clock traces and signal traces and reducing clock trace to reference trace capacitance at identified crossover points. Each clock trace is shielded by ground traces routed on either side of the clock traces. The reducing of clock trace to reference trace capacitance may include narrowing the reference traces at identified crossover points. Narrowing of the reference traces at a crossover point reduces capacitance to compensate for additional capacitance between the clock trace and the signal trace. Narrowing may be performed by trimming or notching at the crossover points. Such capacitive compensation provides clock traces of the clock network with substantially uniform capacitance per unit length.

Abstract: A dynamic logic register including evaluation logic, delay logic, and latching logic. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.

Abstract: A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.

Abstract: A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

Abstract: An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

Abstract: An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node.

Abstract: A domino register including an evaluation circuit, a write circuit, an inverter, a keeper circuit, and output logic. The evaluation circuit pre-charges a first node and evaluates a logic function for controlling a state of the first node when the clock signal goes high. The write circuit drives a second node high if the first node is low and drives the second node low if the first node stays high during evaluation. The inverter inverts the second node to control the state of a third node. The keeper circuit keeps the second node high while the third node and clock signals are both low and keeps the second node low while the third and first nodes are both high. The high and low paths of the keeper circuit are otherwise disabled, including when the write circuit changes state. Thus, the write circuit does not have to overcome a keeper device.

Abstract: A dynamic priority multiplexer including a complementary pair of evaluation devices responsive to a clock signal defining evaluation periods, and multiple evaluation legs coupled in cascade between a top node and a bottom node and arranged in order of priority. The complementary pair includes a pull-up device that pre-charges the top node and a pull-down device that pulls the bottom node low during evaluation. Each higher priority evaluation leg receives a corresponding select signal and a corresponding data signal and includes a corresponding pass device. A select signal, when asserted, enables evaluation of a corresponding data signal and disables a corresponding pass device which disables evaluation by lower priority evaluation legs. The lowest priority evaluation leg includes a pull-down data device that receives a lowest priority data signal and which is coupled between a pass device of a higher priority evaluation leg and the bottom node.

Abstract: A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first preliminary output node and includes a pull-up device and a pull-down device both responsive to the pre-charged node, and a second pull-down device responsive to the clock signal. The keeper circuit is a cross-coupled pair of inverters coupled between the first preliminary output node and a second preliminary output node. The output stage includes a pair of pull-up and pull-down devices for driving an output node. The first pull-up device and the first pull-down device are both responsive to the pre-charged node, and the second pull-up device and the second pull-down device are both responsive to the second preliminary output node.

Abstract: A method of optimizing clock network capacitance of an integrated circuit (IC) including identifying any crossover points between clock traces and signal traces and reducing clock trace to reference trace capacitance at identified crossover points. Each clock trace is shielded by ground traces routed on either side of the clock traces. The reducing of clock trace to reference trace capacitance may include narrowing the reference traces at identified crossover points. Narrowing of the reference traces at a crossover point reduces capacitance to compensate for additional capacitance between the clock trace and the signal trace. Narrowing may be performed by trimming or notching at the crossover points. Such capacitive compensation provides clock traces of the clock network with substantially uniform capacitance per unit length.