Abstract: A computer system and method of operation has a retargeting program and apparatus which permits adding incorrectly targeted processors and a maintenance interface module (MIM) and automatically retargets them for the correct system. Each processor first determines its own system type, and the overall system type. Incorrectly targeted processors wait for retargeting, while correctly targeted processors select a master processor. The master processor retargets all incorrectly targeted processors by transferring an image of its correctly targeted firmware microcode into their RAM to be burned into their firmware. The MIM is retargeted using master processor code. Only accurately targeted or retargeted processors and MIM can be incorporated into the operating system.

Abstract: A block replicate magnetic bubble memory organization is disclosed in which a number of storage loops are arranged between write and read tracks. Data in the read track is supplied to a deskewing circuit under the control of one section of an EAPROM so that the deskewing circuit outputs one page at a time, where each bit of the page is derived from a different storage loop, to a buffer and error correcting circuit which supplies corrected information to a data processing system as long as only one error bit has occurred on a page. If an error does occur in a page, the processor which has stored in it information relating to all of the used and unused loops of the system, controls another section of the EAPROM so that the defective loop will be exchanged for a good loop after a predetermined number of failures have occurred for the particular bad loop. The write side of the EAPROM is subsequently updated by the processor or remote processor that utilizes the read-out data.

Abstract: A beam recombiner is used to parallelize two first order beams emanating from an magneto-optic stripe domain light deflector. One arrangement uses a concave cylindrical mirror with a negative meniscus lens attached thereon to redirect a conjugate beam. The other arrangement uses a concave cylindrical mirror with a cylindrical rod lens placed at the radius of curvature of the mirror to redirect the conjugate beam.

Abstract: A novel optical transmitter/receiver device is described which comprises a source of radiation providing a collimated coherent light beam, such as a laser beam, along a first optical axis; a magneto-optic light deflector device controllably deflecting the beam off the first optical axis in the direction of a target; optical beam expander and collimating lenses transmitting the expanded beam toward the target and receiving the expanded and reflected beam from the target; the reflected beam then being deflected back along the first optical axis to a scraper mirror which optically turns the reflected beam along a viewing axis toward a photo detector.

Abstract: An analog speech signal is sampled of a nominal rate of 6 kilohertz and digitized in a Mu-Law Encoder. The digital output of the Mu-Law Encoder is converted by a microprocessor performing table look-up to linearized pulse code modulation (PCM) samples nominally of eight bits per sample. Using a BSPCM (Block Scaled Pulse Code Modulation) method, in each block of nominally 246 eight-bit PCM samples (representing approximately 41 milliseconds), the maximum and minimum sample values are found and used to calculate a scale factor equal to the maximum sample value minus the minimum sample value, with the difference being then divided by a constant number nominally equaling 16. Then the BSPCM samples are generated from the PCM samples each as a corresponding one PCM sample minus the minimum PCM sample value, the difference being then divided by the scale factor. In effect, the bit rate is reduced by adjusting the step size to follow the local block dynamic range.

Abstract: Apparatus for preventing the writing of data into an MNOS memory during various time intervals, whereby the over-writing and premature fatiguing of the differential voltage separation of the memory cells is prevented. The apparatus comprising an access memory that flags each address when it is first written during a write protect interval so that upon subsequent attempts to write the same address a write abort will occur.