Abstract: Complementary insulated gate field effect transistors are formed in a thin semiconductor layer of a first conductivity type by first forming a dielectric layer on a surface of the semiconductor layer. A polycrystalline support is then formed on the dielectric layer. A lightly doped tub region of a second conductivity type is formed in the semiconductor layer extending to the dielectric layer. The lightly doped tub region is preferably formed by carrying out a conventional diffusion operation, then removing a portion of the thickness of the semiconductor layer which contains the highest dopant concentration. Regions serving as source and drain electrodes of a first and second field effect transistor are then formed in the lightly doped tub region and in the semiconductor layer. Gate electrodes are provided over an insulating layer on the surface of the semiconductor layer to complete fabrication of the complementary devices.