Patents by Inventor Raymond C. Wells

Raymond C. Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6113721
    Abstract: Removing a portion of an active wafer (12) at the edge (18) after the active wafer (12) is bonded to a base wafer (10) prevents chipping of the edge of the active wafer during thinning of the active wafer (12). Grinding and polishing of the edges of the active wafer (12) is preferably performed.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: September 5, 2000
    Assignee: Motorola, Inc.
    Inventors: Frank T. Secco d'Aragona, David D. Oliver, Raymond C. Wells
  • Patent number: 5413952
    Abstract: A method for forming a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. By patterning the high temperature metal nitride layer (16) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal nitride layer (16) and a dielectric layer (17, 27) subsequently formed over the high temperature metal nitride layer (16) is significantly improved. The dielectric layer (17, 27) will adhere to the high temperature metal nitride layer (16) in high temperature environments. In addition, a direct wafer bonded structure having a buried high temperature metal nitride layer (16) and improved thermal conductivity is provided. The structure is suitable for power, logic, and high frequency integrated circuit devices.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: May 9, 1995
    Assignee: Motorola, Inc.
    Inventors: Irenee Pages, Francesco D'Aragona, James A. Sellers, Raymond C. Wells
  • Patent number: 5389579
    Abstract: A method for polishing a single side of a semiconductor wafer (31) is disclosed for improving wafer flatness. A protective layer (32) is formed on one side of the semiconductor wafer (31). The semiconductor wafer (31) is polished on both sides concurrently using double sided polishing equipment (38,41). The protective layer (32) prevents a surface (37) of the semiconductor wafer (31) from being polished while the other unprotected surface (36) is polished thereby producing a single sided polished wafer.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventor: Raymond C. Wells
  • Patent number: 5314107
    Abstract: A method for joining a number of first and second wafers (11,12) having one polished surface in preparation for direct wafer bonding is provided. The method involves placing a number of first (11) and the same number of second (12) wafers into slots (16) of a retainer (14) so that each of the polished surfaces of the number of first wafers (11) is forced to contact one of the polished surfaces of the number of second wafers (12).
    Type: Grant
    Filed: December 31, 1992
    Date of Patent: May 24, 1994
    Assignee: Motorola, Inc.
    Inventors: Frank S. d'Aragona, Raymond C. Wells, Sherry L. F. Helsel
  • Patent number: 5268326
    Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: December 7, 1993
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Frank S. d'Aragona, Francine Y. Robb, Raymond C. Wells
  • Patent number: 5131968
    Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: July 21, 1992
    Assignee: Motorola, Inc.
    Inventors: Raymond C. Wells, Frank S. d'Aragona
  • Patent number: 4655191
    Abstract: A wire saw machine having a wire supply source providing a plurality of strands of wire results in a wire saw system having parallel wires. The wire supply source feed spindle holds a supply source at a slight angle advance to allow the wire to transfer from the supply source to a grooved wire guide in a parallel manner. Two moveable wire guides are used to impart a back and forth motion to the wire over the cutting area and at the same time serve as an intermediate storage area for the wire being used in the cutting area. The wire supply source includes a plurality of individually rotatable wire reels. A friction disc is located between each of the individual wire reels and is held fixed with respect to the spindle.
    Type: Grant
    Filed: March 8, 1985
    Date of Patent: April 7, 1987
    Assignee: Motorola, Inc.
    Inventors: Raymond C. Wells, Thomas J. Hatfield
  • Patent number: 4494523
    Abstract: An improved wire saw is disclosed in which a linear wire storage means comprises a vertically moving carriage. The carriage is supported by the wire, thereby improving the efficiency and production rate of the saw.
    Type: Grant
    Filed: August 5, 1983
    Date of Patent: January 22, 1985
    Assignee: Motorola, Inc.
    Inventor: Raymond C. Wells
  • Patent number: RE36890
    Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: October 3, 2000
    Assignee: Motorola, Inc.
    Inventors: Raymond C. Wells, Frank T. Secco d'Aragona