Abstract: A low-power static random access memory (SRAM) for at-memory architecture is described. The SRAM in at-memory architecture is located adjacent to a Processing Element (PE) so that the same voltage is required at the SE and the SRAM connected to the PE. However, SRAM read/write operation needs different voltage than the PE. Accordingly, selective voltage supplies are described including adaptive voltage supplies (AVS). A bitline precharge level of 0.1V is described for ultra-low power. Moreover, to reduce the number of supply voltages, the bit cell voltage is set at standard cell voltage, Vddc for read, and at a PE operating voltage Vddp for a write.

Abstract: Various devices, circuits and systems including filter sections for creating complex poles are described herein. For example, various circuits including transistors, tuning capacitors and resistors are described. In the circuits, the tuning capacitor is electrically coupled between the gate and source of the transistor, and the resistor is electrically coupled to the gate of the transistor. In one configuration, the circuit input is applied to the gate of the transistor via the resistor, and the output is taken from the source of the transistor. In another configuration, the input is applied to the source of the transistor, and the output is taken from the same source. In yet another configuration, the input is applied at the source of the transistor and the output is taken from the drain of the transistor.

Abstract: A graphics digitizer having a phase-locked-loop, a timing generator, and at least one channel with a reference and bias voltage generator and an analog-to-digital converter is disclosed. In some embodiments, the phase-locked-loop includes a programmable Div/N circuit so that the output frequency of the signal generated by the phase-locked-loop is programmable. In some embodiments, the timing generator generates a HSOUT video signal in response to the HSYNC video signal by sampling the HSYNC video signal with a phase adaptively chosen in response to a programmable phase between the signal generated by the phase-locked-loop and the HSYNC video signal. In some embodiments of the invention the reference and bias voltage generates a reference voltage determined by a digital-to-analog conversion of a value stored in a programmable gain register and generates a bias voltage proportionally to the reference voltage by a current digital-to-analog conversion of a value stored in a programmable offset register.