Patents by Inventor Raymond Devinoy

Raymond Devinoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patch mechanism in embedded controller for memory access
    Patent number: 10824552
    Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Raymond Devinoy, Nicolas Laine
  • PATCH MECHANISM IN EMBEDDED CONTROLLER FOR MEMORY ACCESS
    Publication number: 20140149643
    Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.
    Type: Application
    Filed: April 19, 2013
    Publication date: May 29, 2014
    Applicant: NXP B.V.
    Inventors: Raymond Devinoy, Nicolas Laine