Abstract: A disk drive preamplifier integrated circuit. The integrated circuit comprises a differential output driver configured to drive readback data to an output load, wherein the output driver comprises a differential mode filter configured to filter alternating current of an on-chip power supply.

Abstract: A disk drive preamplifier integrated circuit. The integrated circuit comprises a differential output driver configured to drive readback data to an output load, wherein the output driver comprises a differential mode filter configured to filter alternating current of an on-chip power supply.

Abstract: An apparatus with a differential impedance matched laser diode driver with AC-DC match.

Abstract: One embodiment includes a light-emitting diode (LED) control system. The system includes an LED driver system configured to regulate a control voltage based on a substantially constant reference current and a feedback voltage at a feedback node. The system also includes a digital current source system comprising a plurality of unit current sources that are each coupled to an LED. The plurality of unit current sources can be selectively activated to each provide a given unit current through the LED and to each provide the feedback voltage as an interpolative feedback to the feedback node based on the unit current. The system further includes a current magnitude controller configured to selectively activate the plurality of unit current sources in response to a current magnitude signal.

Abstract: One embodiment includes a light-emitting diode (LED) control system. The system includes an LED driver system configured to regulate a control voltage based on a substantially constant reference current and a feedback voltage at a feedback node. The system also includes a digital current source system comprising a plurality of unit current sources that are each coupled to an LED. The plurality of unit current sources can be selectively activated to each provide a given unit current through the LED and to each provide the feedback voltage as an interpolative feedback to the feedback node based on the unit current. The system further includes a current magnitude controller configured to selectively activate the plurality of unit current sources in response to a current magnitude signal.

Abstract: A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.

Abstract: A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.

Abstract: A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock signal from a source coupled to the sample-and-hold circuit. The frequency of the jittered clock signal is less than frequency of the received RF signal. The random number appears at the output of the sample-and-hold circuit.

Abstract: The power on reset circuit includes: a comparator; a resistor string having a first end coupled to a first supply node of the comparator, a first tap point node coupled to a first input of the comparator, and a second end coupled to a second input of the comparator; and a diode connected transistor device coupled between the second end of the resistor string and a second supply node of the comparator.

Abstract: Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver. The radio frequency energy receiver is operable to receive a radio frequency energy and to convert the radio frequency energy to a DC current. In addition, the device further includes a first clock generator that generates a first clock at a first frequency and second clock generator that generates another clock based on the first clock. The first clock generator includes a duty cycle correction circuit. The second clock has a positive going clock edge for each edge of the first clock.

Abstract: A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage limiter circuit. The voltage limiter generates a limited voltage. A voltage regulator is coupled to the limited voltage for generating a regulated output voltage. The voltage regulator has a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.

Abstract: A write circuit selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected, respectively to the head nodes and the emitters of first and second upper drive transistors. The diodes increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium.

Abstract: A circuit is provided to switch a drive transistor in a write driver circuit controlled by a write control signal to direct write current in a selected direction through an inductive head. Current is selectively conducted from a control region of the drive transistor in response to switching of the write control signal. A first bias circuit limits voltage fluctuation at the control region of the drive transistor. A second bias circuit prevents saturation of the drive transistor.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected respectively the head nodes and the emitters of first and second upper drive transistors. The diodes, which are preferably Schottky diodes, increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium. Additionally, a preferred embodiment of the write driver includes two voltage clamps, each coupled between a respective head node and a first supply node, to limit the magnitude of voltage spikes resulting from self-inductance of the write head.

Abstract: A write driver, having a pair of inputs for receiving write data signals, includes a TTL buffer circuit connected to one input and a PECL buffer circuit connected to both inputs. A detector, responsive to a voltage at one of the inputs, selectively operates either the TTL buffer circuit or the PECL buffer circuit. The detector preferably comprises a comparator, a switching circuit, and two current mirrors. The comparator compares the voltage at one of the inputs to a reference voltage and outputs a signal controlling the switching circuit. The switching circuit enables one of the current mirrors, thereby enabling either the TTL or the PECL buffer circuit. In the preferred embodiment, a Schottky diode isolates the TTL buffer circuit from the PECL buffer circuit.

Abstract: A preamplifier and its associated biasing circuitry for connection to a magnetoresistive sensor having a first end and a second end is disclosed. The biasing circuitry properly biases the preamplifier such that the preamplifier can properly read signals from the sensor. The preamplifier includes a first transistor. A base of the first transistor is connected to the first end of the magnetoresistive sensor. An emitter of the second transistor is connected to the emitter of the first transistor. A collector of the third transistor is connected to the collector of the first transistor. A base of the fourth transistor is connected to the second end of the magnetoresistive sensor, while the collector of the fourth transistor is connected to the collector of the second transistor, and the emitter of the fourth transistor is connected to the emitter of the third transistor. The preamplifier further includes a voltage source and a first and a second resistor.

Abstract: A first differential amplifier circuit is provided having a first and second input terminal suited for connection to a magnetic head. The first differential amplifier circuit includes first and second output terminals for providing a read output signal. A second differential amplifier circuit is provided which has first and second input terminals connected to the first and second input terminals, respectively, the first differential amplifier circuit. The second differential amplifier circuit also includes first and second output terminals. A first feedback capacitor is provided which is connected between the first input terminal of the first differential amplifier circuit and the first output terminal of the second differential amplifier circuit. A second feedback capacitor is provided which is connected between the second input terminal of the first differential amplifier circuit and the second output terminal of the second differential amplifier circuit.

Abstract: A write driver for a two-terminal inductive load comprises an H-bridge switching circuit and a push-pull driver circuit. The H-bridge switching circuit responds to a first mode to conduct a current in a first direction through the inductive load and responds to a second mode to conduct the current in a second direction through the inductive load. The push-pull driver circuit responds to the first mode to push a charge current into a first control node of the H-bridge and responds to the second mode to pull a discharge current from the first control node. In one form, the write driver includes a second push-pull driver circuit responsive to the first mode to pull a discharge current from a second control node and to the second mode to push a charge current into the second control node.