Abstract: A circuit for generating timing signals for clocking the sensing amplifiers of a SRAM memory array having a plurality of memory cells joined in rows by wordlines and in columns by bitlines including a dummy bitline, a plurality of dummy memory cells joined to the dummy bit column, means for accessing a plurality of the dummy memory cells in parallel to generate a bitline charging current significantly greater than a bitline charging current in a typical operative column of the SRAM memory array, a circuit responsive to current in the dummy bitline for generating a timing signal to sense amplifiers for generating output signals from the operative columns of the SRAM.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.

Abstract: A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up means for pulling high the output of the Output Driver and a pull-down means for pulling low the output of the Output Driver. The first pull-up means includes a bipolar transistor. Coupled in parallel with the first pull-up means is a MOS transistor wherein the gate of the MOS transistor is electrically isolated from the base of the bipolar transistor.

Abstract: A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up circuit for pulling high the output of the Output Driver and a pull-down circuit for pulling low the output of the Output Driver. The first pull-up means includes a bipolar transistor. Coupled in parallel with the first pull-up circuit is a MOS transistor wherein the gate of the MOS transistor is electrically isolated from the base of the bipolar transistor.

Abstract: The present electrical circuit functions to couple together circuits which may have different signal operating levels, such as circuits having small-swing ECL operating levels and large-swing TTL operating levels. The present circuit outputs a signal which is virtually unaffected by any non-ideal characteristics of transistors comprising the circuit.

Abstract: The invention relates to an improved CMOS clamped sense amplifier having an input terminal adapted to receive the signal to be sensed. The signal passes through a CMOS input clamp circuit which includes a pair of complementary MOS transistors having their drains coupled together and to the input terminal, and their sources adapted to be coupled respectively to opposite power supply terminals. The input signal also passes to a voltage gain stage coupled to the input terminal and having an output terminal for providing the amplified output signal from the sense amplifier. To achieve the enhanced signal throughput speed, a resistance means is employed, coupled between the gates of the transistors of the CMOS input clamp circuit and the input terminal. Although this resistance reduces the clamping effectiveness of the clamping circuit, it still decreases the overall throughput time through the sense amplifier, thus increasing switching speed.

Abstract: A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.