Abstract: An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.

Abstract: A method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.

Abstract: A novel mode of operation of an array of MNOS memory transistors is provided which employs the punch through mode of erase and enables a single transistor memory cell to be used. It being arranged that all `bits` are written into the `1` state and bits are selectively erased to provide the required data pattern.