Abstract: A tamper detection arrangement for use within an integrated circuit (1), the arrangement comprising: at least one input capacitor (4) having a first capacitance value; a feedback capacitor (5) having a second capacitance value; a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier operable to detect a change in the capacitance values between the at least one input capacitor and the feedback capacitor; and a protective shield to protect a sensitive area (2) of the integrated circuit from tampering, the shield being provided by the at least one input capacitor (4).

Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

Abstract: A tamper detection arrangement for use within an integrated circuit (1), the arrangement comprising: at least one input capacitor (4) having a first capacitance value; a feedback capacitor (5) having a second capacitance value; a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier operable to detect a change in the capacitance values between the at least one input capacitor and the feedback capacitor; and a protective shield to protect a sensitive area (2) of the integrated circuit from tampering, the shield being provided by the at least one input capacitor (4).

Abstract: A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.

Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.

Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Abstract: Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits 3 and 5, respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) 1 is applied across a pair of series connected resistors 7 and 9, and to the inputs of the amplifiers 3 and 5. The common mode voltage signal 11 is fed to the inputs of third and fourth amplifiers 15 and 17. The third and fourth amplifiers 15 and 17 ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.

Abstract: A photodiode detection circuit using a transimpedance amplifier circuit is disclosed. Overload current from the photodiode is diverted away from the amplifier to a voltage supply, e.g. ground, through an overload protection diode connected in series with the photodiode. A differential structure is also disclosed.

Abstract: There is disclosed a level shift circuit which has a differential input, for receiving input signals, and a differential output, for supplying output signals derived from the input signals. The level shift circuit further includes a control level setting input, and a feedback circuit for setting a common mode level of the output signals to a level set on the control level setting input. This allows the output common mode to be set accurately, independently of the input common mode.

Abstract: Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits 3 and 5, respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) 1 is applied across a pair of series connected resistors 7 and 9, and to the inputs of the amplifiers 3 and 5. The common mode voltage signal 11 is fed to the inputs of third and fourth amplifiers 15 and 17. The third and fourth amplifiers 15 and 17 ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.