Abstract: A memory system for B frames of pixel data, where each B frame includes a plurality of sections, and where each of the plurality of sections includes pixel data corresponding to the top and bottom fields of a frame. The memory system includes a memory organized into a plurality of segments for storing the pixel data, where the number of segments equals the number of frame sections plus two additional segments. However, each of the segments is half the size of a frame section. The memory system also includes a segmentation device for receiving and separating pixel data according to the top and bottom fields of each frame. The segmentation device tracks the segments to determine two available segments of said memory, and for each section of each frame, stores pixel data from the top field into one of the available segments and stores pixel data from the bottom field into the other available segment of the memory.

Abstract: An apparatus and method for improved clock distribution and control in an integrated circuit which minimizes clock skew between various parts of the integrated circuit chip. Clock loads are evenly distributed between tributaries. Capacitive loading is utilized to balance any differences between tributaries and for minimizing clock skew throughout the integrated circuit.