Abstract: An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.

Abstract: A protection circuit for a parallel power system having at least two parallel coupled voltage regulators is disclosed. The protection circuit includes at least two isolation control circuits, each control circuit being coupled to a respective voltage regulator. Each isolation control circuit includes a current sense circuit for sensing current polarity at an output of the respective voltage regulator, and a controller for automatically isolating the respective voltage regulator when an over-voltage condition exists at an output of the parallel power system and a positive current polarity is sensed at the output of the respective voltage regulator. The at least two isolation control circuits isolate only a voltage regulator having positive current outflow during the over-voltage condition. In one embodiment, each isolation control circuit further includes an over-voltage detection circuit for detecting when the over-voltage condition exists at the output of the parallel power system.

Abstract: An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.

Abstract: A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power shut off to provide service signals. The service logic also includes an auxiliary energy source selectively engageable to provide auxiliary power to the memory and control component during power shut off and to enable providing of service signals through the indicator(s).

Abstract: A protection circuit for a parallel power system having at least two parallel coupled voltage regulators is disclosed. The protection circuit includes at least two isolation control circuits, each control circuit being coupled to a respective voltage regulator. Each isolation control circuit includes a current sense circuit for sensing current polarity at an output of the respective voltage regulator, and a controller for automatically isolating the respective voltage regulator when an over-voltage condition exists at an output of the parallel power system and a positive current polarity is sensed at the output of the respective voltage regulator. The at least two isolation control circuits isolate only a voltage regulator having positive current outflow during the over-voltage condition. In one embodiment, each isolation control circuit further includes an over-voltage detection circuit for detecting when the over-voltage condition exists at the output of the parallel power system.

Abstract: A method for data access via an inter-integrated circuit (I2C) protocol. The method includes receiving an I2C read command at an I2C slave device, where the I2C read command is from an I2C master device. The method also includes reading stored data from a storage device in response to receiving an I2C read command. The stored data is at a first location in the storage device corresponding to a value in a register array pointer in the I2C slave device. The stored data is transmitted to the I2C master device in response to the reading. The method also includes receiving an I2C write command at the I2C slave device, where the I2C write command is from the I2C master device and the write command includes master data and a slave device register address. The master data is written to the storage device in response to receiving the I2C write command, with the master data being written at a second location in the storage device corresponding to the slave device register address.

Abstract: A system and method for providing an interface between a master device referenced at a first voltage and a slave device referenced at a second voltage. The system includes a bidirectional communications link between the master device and the slave device and a bidirectional transceiver device in the communications link for decomposing bidirectional signals on the communications link into transmissions from the slave device to the master device onto a first bus, and transmissions from the master device to the slave device onto a second bus. A first isolation device is included in the bidirectional link and connected to the first bus for transmitting signals over the bidirectional link from the master device referenced at the first voltage to the slave device referenced at the second voltage.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: A communication system, method and program product are provided for establishing an extended bidirectional communication bus between a first device and a second device. The communication system includes decomposition logic for decomposing a single line, bidirectional data communication bus into a unidirectional transmit data communication bus and a unidirectional receive data communication bus. A differential communication subsystem is connected to the two unidirectional buses for extending the length thereof, and recomposition circuitry is connected to the differential communication subsystem for recombining the extended unidirectional transmit data communication bus and the extended unidirectional receive data communication bus to reestablish the single line, bidirectional data communication bus. The decomposition logic, differential communication subsystem and recomposition circuitry are implemented transparent to the first device and the second device and without use of a data direction control line.

Abstract: One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.

Abstract: An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.

Abstract: A system and a method for starting a brushless DC motor are provided. The method includes applying commutation pulses to at least two phase coils to induce a rotor to rotate to a starting position and then de-energizing the at least two phase coils. The method further includes applying commutation pulses to at least two phase coils to induce the rotor to rotate from the starting position in a predetermined direction. The method further includes de-energizing all phase coils for a first time interval after the rotor is rotating and sampling a back EMF signal in at least one of the phase coils to determine a first value indicative of an electrical period of the back EMF signal or a portion of an electrical period of the back EMF signal. Finally, the method includes applying commutation pulses to at least two phase coils for a second time interval, the second time interval being based on the first value.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: A communication system for establishing bidirectional, asynchronous communication between a first device and a second device. The system includes first asynchronous encoder logic and second asynchronous encoder logic for controlling the state of the communication system such that bidirectional communication is enabled without a direction control line.