Abstract: Computer-implemented methods of operating an augmented reality device can involve capturing camera images, processing the camera images, and displaying virtual display images. The camera images can be captured automatically using a camera disposed within an augmented reality device worn by a user. The camera images can be processed automatically using a processor located within the augmented reality device. The virtual display images can be displayed automatically to the user within the augmented reality device while the user is looking through the augmented reality device and simultaneously viewing real objects through the augmented reality device. The virtual display images can be based on the processed camera images. Additional steps can include accepting a first user input, storing camera image(s) on a memory located within the augmented reality device based on the first input, accepting a second user input, and displaying stored image(s) to the user based on the second input.

Abstract: Computer-implemented methods of operating an augmented reality device can involve capturing camera images, processing the camera images, and displaying virtual display images. The camera images can be captured automatically using a camera disposed within an augmented reality device worn by a user. The camera images can be processed automatically using a processor located within the augmented reality device. The virtual display images can be displayed automatically to the user within the augmented reality device while the user is looking through the augmented reality device and simultaneously viewing real objects through the augmented reality device. The virtual display images can be based on the processed camera images. Additional steps can include accepting a first user input, storing camera image(s) on a memory located within the augmented reality device based on the first input, accepting a second user input, and displaying stored image(s) to the user based on the second input.

Abstract: Computer-implemented methods of operating an augmented reality device can involve capturing camera images, processing the camera images, and displaying virtual display images. The camera images can be captured automatically using a camera disposed within an augmented reality device worn by a user. The camera images can be processed automatically using a processor located within the augmented reality device. The virtual display images can be displayed automatically to the user within the augmented reality device while the user is looking through the augmented reality device and simultaneously viewing real objects through the augmented reality device. The virtual display images can be based on the processed camera images. Additional steps can include accepting a first user input, storing camera image(s) on a memory located within the augmented reality device based on the first input, accepting a second user input, and displaying stored image(s) to the user based on the second input.

Abstract: An augmented reality device can include an outer housing, an attachment component, a camera, and a display arrangement. The outer housing can have a transparent front and back arranged to allow a user to see therethrough. The attachment component can removably attach the augmented reality device to user eyewear. The camera can capture images through the outer housing front. The display arrangement can provide a virtual display at an angle to the user looking through the augmented reality device. The display arrangement can include an image emitting component, a prism component, a projecting optic component, a combining optic component, and a unibody optics enclosure. The augmented reality device can also include a processor and a memory configured to store and retrieve buffer clips of captured images, and a wireless communication component configured for communications with outside devices.

Abstract: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Abstract: A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC.

Abstract: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Abstract: An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

Abstract: A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages are supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.