Patents by Inventor Raymond Hoiman Hung

Raymond Hoiman Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038859
    Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang
  • Publication number: 20220231137
    Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang
  • Patent number: 11355391
    Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 7, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Feiyue Ma, Kai Wu, Yu Lei, Kazuya Daito, Yi Xu, Vikash Banthia, Mei Chang, He Ren, Raymond Hoiman Hung, Yakuan Yao, Avgerinos V. Gelatos, David T. Or, Jing Zhou, Guoqiang Jian, Chi-Chou Lin, Yiming Lai, Jia Ye, Jenn-Yue Wang
  • Patent number: 11037838
    Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 15, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xuebin Li, Schubert S. Chu, Errol Antonio C. Sanchez, Patricia M. Liu, Gaurav Thareja, Raymond Hoiman Hung
  • Publication number: 20200303250
    Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 24, 2020
    Inventors: Xi CEN, Feiyue MA, Kai WU, Yu LEI, Kazuya DAITO, Yi XU, Vikash BANTHIA, Mei CHANG, He REN, Raymond Hoiman HUNG, Yakuan YAO, Avgerinos V. GELATOS, David T. OR, Jing ZHOU, Guoqiang JIAN, Chi-Chou LIN, Yiming LAI, Jia YE, Jenn-Yue WANG
  • Patent number: 10615034
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Zheng, Avgerinos V. Gelatos, Anshul Vyas, Raymond Hoiman Hung
  • Publication number: 20190326115
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Application
    Filed: December 26, 2018
    Publication date: October 24, 2019
    Inventors: Bo Zheng, Avgerinos V. Gelatos, Anshul Vyas, Raymond Hoiman Hung
  • Patent number: 10163630
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 25, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Zheng, Avgerinos V. Gelatos, Anshul Vyas, Raymond Hoiman Hung
  • Publication number: 20180122945
    Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.
    Type: Application
    Filed: April 18, 2017
    Publication date: May 3, 2018
    Inventors: Chih-Yang CHANG, Raymond Hoiman HUNG, Tatsuya E. SATO, Nam Sung KIM, Shiyu SUN, Bingxi Sun WOOD
  • Patent number: 9960275
    Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 1, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Chih-Yang Chang, Raymond Hoiman Hung, Tatsuya E. Sato, Nam Sung Kim, Shiyu Sun, Bingxi Sun Wood
  • Publication number: 20170365468
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Application
    Filed: August 11, 2017
    Publication date: December 21, 2017
    Inventors: Bo ZHENG, Avgerinos V. GELATOS, Anshul VYAS, Raymond Hoiman HUNG
  • Patent number: 9735009
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 15, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Zheng, Avgerinos V. Gelatos, Anshul Vyas, Raymond Hoiman Hung
  • Publication number: 20160079062
    Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 17, 2016
    Inventors: Bo ZHENG, Avgerinos V. GELATOS, Anshul VYAS, Raymond Hoiman HUNG
  • Patent number: 8293460
    Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 23, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Hui W. Chen, Chorng-Ping Chang, Yongmei Chen, Huixiong Dai, Jiahua Yu, Susie X. Yang, Xumou Xu, Christopher D. Bencher, Raymond Hoiman Hung, Michael P. Duane, Christopher Siu Wing Ngai, Jen Shu, Kenneth MacWilliams
  • Publication number: 20090311635
    Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.
    Type: Application
    Filed: December 19, 2008
    Publication date: December 17, 2009
    Inventors: HUI W. CHEN, CHORNG-PING CHANG, YONGMEI CHEN, HUIXIONG DAI, JIAHUA YU, SUSIE X. YANG, XUMOU XU, CHRISTOPHER D. BENCHER, RAYMOND HOIMAN HUNG, MICHAEL P. DUANE, CHRISTOPHER SIU WING NGAI, JEN SHU, KENNETH MACWILLIAMS