Patents by Inventor Raymond Horton
Raymond Horton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11587860Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.Type: GrantFiled: March 8, 2020Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: John Knickerbocker, Bing Dang, Raymond Horton, Joana Maria
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Patent number: 10903153Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.Type: GrantFiled: November 18, 2018Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: John Knickerbocker, Bing Dang, Raymond Horton, Joana Maria
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Publication number: 20200211947Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.Type: ApplicationFiled: March 8, 2020Publication date: July 2, 2020Inventors: John Knickerbocker, Bing Dang, Raymond Horton, Joana Maria
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Publication number: 20200161230Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.Type: ApplicationFiled: November 18, 2018Publication date: May 21, 2020Inventors: John Knickerbocker, Bing Dang, Raymond Horton, Joana Maria
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Publication number: 20080067628Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mote vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step.Type: ApplicationFiled: October 31, 2007Publication date: March 20, 2008Applicant: International Business Machines CorporationInventors: Raymond Horton, John Knickerbocker, Edmund Sprogis, Cornelia Tsang
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Publication number: 20080036084Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.Type: ApplicationFiled: January 30, 2006Publication date: February 14, 2008Applicant: International Business Machines CorporationInventors: Leena Buchwalter, Paul Andry, Matthew Farinelli, Sherif Goma, Raymond Horton, Edmund Sprogis
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Publication number: 20070222065Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Applicant: International Business Machines CorporationInventors: Paul Andry, Leena Buchwalter, Raymond Horton, John Knickerbocker, Cornelia Tsang, Steven Wright
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Publication number: 20070035030Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: ApplicationFiled: August 11, 2005Publication date: February 15, 2007Applicant: International Business Machines CorporationInventors: Raymond Horton, John Knickerbocker, Edmund Sprogis, Cornelia Tsang
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Publication number: 20060255480Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jon Casey, Michael Berger, Leena Buchwalter, Donald Canaperi, Raymond Horton, Anurag Jain, Eric Perfecto, James Tornello
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Publication number: 20060075434Abstract: A television system for receiving a plurality of digitally-encoded television programs includes circuitry for selecting a particular digital data transmission channel from a plurality of digital data transmission channels containing a desired digitally-encoded television program in response to a control signal, at least one of the data transmission channels also including television program schedule data. The system also includes user-operable data entry circuitry for entering data, and a controller for generating the above-noted control signal in response to user-entered data. The controller selects a virtual channel from a plurality of virtual channels in response to user-entered data, each virtual channel being subject to reassignment to a different one of said a plurality of digital data transmission channels, the television program schedule data defining the relationship of each of the television programs to respective ones of the plurality of digital data transmission channels.Type: ApplicationFiled: June 23, 2005Publication date: April 6, 2006Inventors: John Chaney, Bill Beyers, Michael Johnson, James Hailey, Kevin Bridgewater, Michael Deiss, Raymond Horton
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Publication number: 20060027934Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: October 3, 2005Publication date: February 9, 2006Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
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Publication number: 20050121768Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
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Publication number: 20050106834Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.Type: ApplicationFiled: November 3, 2003Publication date: May 19, 2005Inventors: Paul Andry, Jon Casey, Raymond Horton, Chiraq Patel, Edmund Sprogis, Brian Sundlof