Abstract: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element.

Abstract: A circuit that employs an anti-tamper sensor includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element. The decoy coupling element will cause the circuit element not to operate normally if the decoy coupling element has a selected physical property of the selective coupling element in the first state.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element.

Abstract: A circuit that employs an anti-tamper sensor includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element. The decoy coupling element will cause the circuit element not to operate normally if the decoy coupling element has a selected physical property of the selective coupling element in the first state.

Abstract: A method for conserving energy in a computing unit and transferring data between the computing unit and an external source. The computing unit is in a power saving mode. The method includes receiving at the computing unit a request from an external source, determining which components of the computing unit are required to respond to the request, selectively activating, from the power saving mode, the components of the computing unit necessary to respond the request, and responding to the request using the selectively activated components of the computing unit. As one example, the computing unit may comprise a laptop, and the external source may comprise a PDA, and the request may include a request from the PDA to retrieve data from or store data on the laptop.

Abstract: A method for conserving energy in a computing unit and transferring data between the computing unit and an external source. The computing unit is in a power saving mode. The method includes receiving at the computing unit a request from an external source, determining which components of the computing unit are required to respond to the request, selectively activating, from the power saving mode, the components of the computing unit necessary to respond the request, and responding to the request using the selectively activated components of the computing unit. As one example, the computing unit may comprise a laptop, and the external source may comprise a PDA, and the request may include a request from the PDA to retrieve data from or store data on the laptop.

Abstract: A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

Abstract: A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

Abstract: A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

Abstract: A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

Abstract: System and method reading data from storage by speculatively accessing storage and overlapping data bus access with status determination, thereby reducing storage read access latency. Also, a system and method is provided for reducing storage read access latency by accessing a data bus substantially simultaneously with availability of data from storage. Upon receipt of a storage read request, and before status determination, the requested data is read from storage. Optionally, depending upon bus architecture or the need to minimize control circuitry, control of the data bus may speculatively be sought so that data may be loaded to the data bus upon availability from main storage, still whether or not status has been resolved. Subsequently, if status cancels the read request, further data bus loading is terminated.

Abstract: An address translation mechanism that allows for the creation, use, and purging of Translation Lookaside Buffer (TLB) entries associated to a unique task (virtual machine or guest). This association between guest and TLB entry allows for reuse of guest TLB entries (sets) in a multitasking system, quick purging of TLB entries during transition between address translation states, and quick restoration of control program TLB entries.The address translation mechanism as described herein must contain, at a minimum, a translation lookaside buffer; each entry must contain, at least: a absolute address field, a virtual address field and a translation mode indicator (TMI); a guest TMI table having entries containing a unique identifier to a guest and an associated TMI value; and a TMI register that holds the currently valid TMI.

Abstract: An instruction processing unit (IPU) and a storage array, a storage-to-instruction-processing-unit interface, including a hardware accelerator for cross-boundary storage access with a cross-boundary buffer for providing residual read and write data in support of high speed block concurrent accessing of multi-word operands of a computer system. A cross-boundary buffer (CBB) is used, coupled to a write rotating shifter, a write merger (WMERGE) and a write merge controller (WMCTL) which is coupled for an input to said control register (CREG) for sequencing data transmitted on the data bus for merger with data contained in the cross-boundary buffer (CBB) by the write merger before it is latched in a data bus out register, and for simultaneously also latching the data in the cross-boundary buffer (CBB), and for writing data from the data bus out register into the storage array in the next clock cycle of the instruction processor at the doubleword address addressed.