Abstract: An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.

Abstract: A method, for producing a multi-layer metallization pattern (macro) for a custom sized memory embedded on a masterslice, is disclosed. The memory has "n" addresses and stores "m" bits at each address. Specifically, the memory relies on using macros for a "seed" portion and a "stitch" portion of the memory. The seed portion is a small complete memory. The seed contains all the ancillary support circuitry, e.g. address decoders and true/complement generators, used by the entire embedded memory and a small amount of memory locations, typically having "n" rows each one or two bits wide, with their associated data transfer circuits. A "stitch" is one column of "n" memory locations and the data transfer circuits required to serve these locations.