Abstract: A semiconductor device having a semiconductor body comprising an active area and a termination structure surrounding the active area, and a method for the manufacture thereof. The invention particularly concerns a termination structure for such devices having trenched electrodes in the active area. The termination structure comprises a plurality of lateral trench-gate transistor devices connected in series and extending from the active area towards a peripheral edge of the semiconductor body. The lateral devices are arranged such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices. The termination structure is compact and features of the structure are susceptible for formation in the same process steps as features of the active area.

Abstract: A semiconductor device having a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area, and a method for the manufacture thereof. The invention particularly concerns a termination structure for such devices having trenched electrodes in the active area. The termination structure comprises a plurality of lateral trench-gate transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body. The lateral devices are arranged such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices. The termination structure is compact and features of the structure are susceptible for formation in the same process steps as features of the active area.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (FIG. 14) for supplying a regulated output voltage.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: A semiconductor device has a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area. The termination structure comprises a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode. The termination structure (16) is capable of withstanding higher voltages in a compact manner and features thereof are susceptible to fabrication in the same process steps as features of the active area (7).

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.

Abstract: In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned with respect to each other by providing spacers (52) to form a narrow window (52a) at a wider window (51a) in a mask pattern (51, 51s) that masks where the Schottky barrier (80) is to be formed. The trenched insulated electrode (11s) is formed by etching a trench (20) at the narrow window (52a) and by providing insulating material (17) and then electrode material (11s) in the trench. The guard region (15s) is provided by introducing dopant (61) via the wider window (51a). The mask pattern (51, 51s) masks the underlying body portion against this dopant introduction and is sufficiently wide (y8) to prevent the dopant (61) from extending laterally into the area where the Schottky barrier (80) is to be formed.

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: A two-terminal self-powered synchronous rectifier (ASR) is provided, together with two-terminal or three-terminal packaged devices that can replace an output diode rectifier (D) in a switched mode power supply. The synchronous rectifier comprises a field-effect transistor (M) having its source-drain path in a first arm (11) between the two rectifier terminals (A,K), normally a parallel diode (BD) in a second arm (12), a gate-control circuit (GC) connected to a gate electrode (g) of the transistor (M) for switching the transistor (M) synchronously on and off in accordance with voltage reversal at the two rectifier terminals (A,K), and a charge pump (C,R; C,R,C2,R2) in a third parallel arm for powering the control circuit from the power signal being rectified by the rectifier.

Abstract: Semiconductor devices are known comprising a multiple p-n junction RESURF semiconductor material (10) that provides a voltage-sustaining space-charge zone when depleted from a blocking junction (40). Charge balance is important in the alternating p-type (11) and n-type (12) regions which together provide the voltage-sustaining space-charge zone. The invention provides a low-cost yet reliable way of manufacturing such a material (10), and also devices with such a material (10). A p-type silicon body (100) having an acceptor doping concentration (Na) for the p-type regions (11) of the material is subjected to irradiation with collimated beams (152) of thermal neutrons (150) at window areas (52) in a mask (50) so as to form the n-type regions (12) by transmutation of silicon atoms into phosphorus. A well-defined and controllable phosphorus doping concentration to balance the low acceptor concentration of the p-type regions (11) is achievable in this manner, even when the acceptor concentration is of boron.

Abstract: A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer (21) is doped to have a gate region (23) arranged over the body (7), a field plate region (25) arranged over the drift region 13 and at least one p-n junction (26) forming at least one diode between the field plate region (25) and the gate region (23). A source contact (39) is connected to both the source (9) and the field plate region (25).

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window (18a) for a source electrode (33) can be self-aligned to a narrow trench (20) containing the trench-gate (11). Thereby, the channel-accommodating region (15) can also be provided after forming the trench-gate (11), and with very good control of its doping concentration (Na; p) adjacent to the trench (20). To achieve this control, its dopant is provided after removing the spacers (52) from the mask (51) so as to form a doping window (51b), which may also be used for the source dopant, adjacent to the trench-gate (11). A high energy dopant implant (61) or other doping process provides this channel dopant adjacent to the trench (20) and extending laterally below the mask (51,51n).

Abstract: Trench-gate field-effect transistors, for example power MOSFETs, are disclosed having trenched electrode configurations (11,23) that permit fast switching of the transistor, while also providing over-voltage protection for the gate dielectric (21) and facilitating manufacture. The gate electrode (11) comprising a semiconductor material of one conductivity type (n) is present in an upper part of a deeper insulated trench (20,21) that extends into a drain region (14,14a) of the transistor. A lower electrode (23) connected to a source (13,33) of the transistor is present in the lower part of the trench. This lower electrode (23) comprises a semiconductor material of opposite conductivity type (p) that adjoins the semiconductor material of the gate electrode (11) to form a p-n junction (31) between the gate electrode (11) and the lower electrode (23). The p-n junction (31) provides a protection diode (D) between the gate electrode (11) and the source (13,33).

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned with respect to each other by providing spacers (52) to form a narrow window (52a) at a wider window (51a) in a mask pattern (51, 51s) that masks where the Schottky barrier (80) is to be formed. The trenched insulated electrode (11s) is formed by etching a trench (20) at the narrow window (52a) and by providing insulating material (17) and then electrode material (11s) in the trench. The guard region (15s) is provided by introducing dopant (61) via the wider window (51a). The mask pattern (51, 51s) masks the underlying body portion against this dopant introduction and is sufficiently wide (y8) to prevent the dopant (61) from extending laterally into the area where the Schottky barrier (80) is to be formed.

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).