Patents by Inventor Raymond J. Harrington
Raymond J. Harrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9298249Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.Type: GrantFiled: March 11, 2013Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
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Patent number: 9021097Abstract: A method, system and computer program product for managing and deploying physical and virtual environments across multiple hardware platforms. A single unit, referred to herein as a cloud construction block, contains both the hardware and software components used to build a cloud computing environment. By having such a single unit contain both the hardware and software components needed to build a cloud computing environment, the user no longer needs to purchase and integrate different hardware and software components. Furthermore, the cloud construction block contains modular pieces of hardware, such as compute hardware, memory hardware, storage hardware and network hardware, that are integrated with management software configured to manage both the hardware and the cloud computing environment in a seamlessly integrated package. Since there is a single management system, the management software allows the user to manage the modular pieces of hardware via a single user interface.Type: GrantFiled: May 8, 2012Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Rohith K. Ashok, Thomas M. Brey, Raymond J. Harrington, Matt R. Hogstrom, Matthew J. Sheard
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Patent number: 8984134Abstract: A method, system and computer program product for managing and deploying physical and virtual environments across multiple hardware platforms. A single unit, referred to herein as a cloud construction block, contains both the hardware and software components used to build a cloud computing environment. By having such a single unit contain both the hardware and software components needed to build a cloud computing environment, the user no longer needs to purchase and integrate different hardware and software components. Furthermore, the cloud construction block contains modular pieces of hardware, such as compute hardware, memory hardware, storage hardware and network hardware, that are integrated with management software configured to manage both the hardware and the cloud computing environment in a seamlessly integrated package. Since there is a single management system, the management software allows the user to manage the modular pieces of hardware via a single user interface.Type: GrantFiled: May 7, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Rohith K. Ashok, Thomas M. Brey, Raymond J. Harrington, Matt R. Hogstrom, Matthew J. Sheard
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Publication number: 20130297773Abstract: A method, system and computer program product for managing and deploying physical and virtual environments across multiple hardware platforms. A single unit, referred to herein as a cloud construction block, contains both the hardware and software components used to build a cloud computing environment. By having such a single unit contain both the hardware and software components needed to build a cloud computing environment, the user no longer needs to purchase and integrate different hardware and software components. Furthermore, the cloud construction block contains modular pieces of hardware, such as compute hardware, memory hardware, storage hardware and network hardware, that are integrated with management software configured to manage both the hardware and the cloud computing environment in a seamlessly integrated package. Since there is a single management system, the management software allows the user to manage the modular pieces of hardware via a single user interface.Type: ApplicationFiled: May 8, 2012Publication date: November 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rohith K. Ashok, Thomas M. Brey, Raymond J. Harrington, Matt R. Hogstrom, Matthew J. Sheard
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Publication number: 20130297772Abstract: A method, system and computer program product for managing and deploying physical and virtual environments across multiple hardware platforms. A single unit, referred to herein as a cloud construction block, contains both the hardware and software components used to build a cloud computing environment. By having such a single unit contain both the hardware and software components needed to build a cloud computing environment, the user no longer needs to purchase and integrate different hardware and software components. Furthermore, the cloud construction block contains modular pieces of hardware, such as compute hardware, memory hardware, storage hardware and network hardware, that are integrated with management software configured to manage both the hardware and the cloud computing environment in a seamlessly integrated package. Since there is a single management system, the management software allows the user to manage the modular pieces of hardware via a single user interface.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Applicant: International Business Machines CorporationInventors: Rohith K. Ashok, Thomas M. Brey, Raymond J. Harrington, Matt R. Hogstrom, Matthew J. Sheard
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Patent number: 8527795Abstract: A method, system, and computer usable program product for improving processor performance during power supply failure are provided in the illustrative embodiments. A throttled condition of a processor is detected in a data processing system. A voltage of the electrical power being provided to the processor is reduced. The processor is un-throttled. Additionally, a frequency of electrical power being provided to the processor may also be reduced. A determination is made whether a condition that caused the throttling has been corrected. In response to the condition having been corrected, the frequency is returned to normal frequency and the voltage is returned to normal voltage. The reducing the frequency operation and reducing the voltage operation may each be performed by distinct components communicating over a data network external to the data processing system.Type: GrantFiled: September 30, 2008Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Derek Lee Howard, Martha Ann Broyles, Peter Adam Wendling, Raymond J Harrington, Todd Jon Rosedahl
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Patent number: 8457805Abstract: A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.Type: GrantFiled: April 16, 2010Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Andreas Bieswanger, Andrew Geissler, Raymond J Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
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Patent number: 8452991Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.Type: GrantFiled: August 20, 2009Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
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Publication number: 20110257802Abstract: A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Inventors: ANDREAS BIESWANGER, Andrew J. Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
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Patent number: 7983168Abstract: One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.Type: GrantFiled: April 7, 2009Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Eileen M. Behrendt, Jeffrey R. Biamonte, Raymond J. Harrington
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Publication number: 20110047350Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: International Buisness Machines CorporationInventors: Andrew Geissler, Raymond J. Harrington, Hye-Young McCreary, Freeman Leigh Rawson, III, Malcolm Scott Ware
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Patent number: 7805618Abstract: A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power shut off to provide service signals. The service logic also includes an auxiliary energy source selectively engageable to provide auxiliary power to the memory and control component during power shut off and to enable providing of service signals through the indicator(s).Type: GrantFiled: February 17, 2006Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Kevin R. Covi, Gerald J. Fahr, Raymond J. Harrington, Raymond A. Longhi, Edward J. Seminaro
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Patent number: 7787222Abstract: A protection circuit for a parallel power system having at least two parallel coupled voltage regulators is disclosed. The protection circuit includes at least two isolation control circuits, each control circuit being coupled to a respective voltage regulator. Each isolation control circuit includes a current sense circuit for sensing current polarity at an output of the respective voltage regulator, and a controller for automatically isolating the respective voltage regulator when an over-voltage condition exists at an output of the parallel power system and a positive current polarity is sensed at the output of the respective voltage regulator. The at least two isolation control circuits isolate only a voltage regulator having positive current outflow during the over-voltage condition. In one embodiment, each isolation control circuit further includes an over-voltage detection circuit for detecting when the over-voltage condition exists at the output of the parallel power system.Type: GrantFiled: June 27, 2007Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Kevin R. Covi, Raymond J. Harrington, Robert P. Makowicki, Steven G. Shevach, Dale F. Soreson, Brain C. Tucker
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Patent number: 7715215Abstract: Control of an AC-to-DC power supply assembly fed by a three-phase AC source is provided by: determining whether the power supply assembly includes greater than three single-phase power regulators feeding a common load, with multiple regulators being connected in parallel across a common phase of the AC source, and if so, summing currents provided by the regulators to the common load; and ascertaining whether the summed current is less than a predefined threshold, and if yes, operating the power supply assembly in a line balance mode to maintain power drawn on the phases of the AC source in balance, and if greater than the predefined threshold, operating the power supply assembly in a maximize power mode wherein power is provided to the common load without maintaining power drawn on the phases of the AC source in balance.Type: GrantFiled: January 29, 2009Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Frank E. Bosco, Kevin R. Covi, Anthony J. Cozzolino, Gary F. Goth, Raymond J. Harrington, Peter A. Hein, Raymond A. Longhi, Edward J. Seminaro, Peter A. Wendling
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Publication number: 20100083007Abstract: A method, system, and computer usable program product for improving processor performance during power supply failure are provided in the illustrative embodiments. A throttled condition of a processor is detected in a data processing system. A voltage of the electrical power being provided to the processor is reduced. The processor is un-throttled. Additionally, a frequency of electrical power being provided to the processor may also be reduced. A determination is made whether a condition that caused the throttling has been corrected. In response to the condition having been corrected, the frequency is returned to normal frequency and the voltage is returned to normal voltage. The reducing the frequency operation and reducing the voltage operation may each be performed by distinct components communicating over a data network external to the data processing system.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derek Lee Howard, Martha Ann Broyles, Peter Adam Wendling, Raymond J. Harrington, Todd Jon Rosedahl
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Patent number: 7681073Abstract: An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.Type: GrantFiled: October 28, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Gary D. Anderson, Gerald J. Fahr, Raymond J. Harrington
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Patent number: 7644216Abstract: A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket.Type: GrantFiled: April 16, 2007Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Gerald J. Fahr, Raymond J. Harrington, Roger A. Rippens, Donald J. Swietek
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Publication number: 20090196295Abstract: One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.Type: ApplicationFiled: April 7, 2009Publication date: August 6, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eileen M. Behrendt, Jeffrey R. Biamonte, Raymond J. Harrington
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Publication number: 20090125659Abstract: A program and device for data access via an inter-integrated circuit (I2C) protocol are provided, which includes receiving an I2C read command at an I2C slave device from an I2C master device, and the I2C read command at the I2C slave device is altered such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from internal memory of I2C slave device. An I2C write command having master data and a slave device register address is intended to write to the internal memory of the I2C slave device, and I2C write command at the I2C slave device is altered such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to internal memory of the I2C slave device.Type: ApplicationFiled: January 16, 2009Publication date: May 14, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eileen M. Behrendt, Jeffrey R. Biamonte, Raymond J. Harrington, Timothy M. Trifilo
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Patent number: 7522524Abstract: One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.Type: GrantFiled: April 29, 2004Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Eileen M. Behrendt, Jeffrey R. Biamonte, Raymond J. Harrington