Abstract: A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) (10) which has at least as many address locations as there are channels. A word counter addresses the RAM (10) which provides as its outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM (20) which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block (30) which selectively fills a shift register (40,42) used to drive the parallel data output bus (32). A strobe pulse is also generated which enables a decoder (34) to select the appropriate peripheral device using the encoded device number.

Abstract: The memory-based frame synchronizer comprises a serial-to-parallel converter which converts a serial input data stream to a constantly changing parallel data output. This parallel data output is supplied to programmable sync word recognizers each consisting of a multiplexer (18, 20, 22) and a random access memory (RAM) (38, 40, 42). The multiplexer is connected to both the parallel data output and an address bus (24) which may be connected to a microprocessor or computer for purposes of programming the sync word recognizer. The RAM is used as an associative memory or decoder and is programmed with the pattern of binary 1's and 0's necessary to identify a specific sync word. The RAM produces an output when the address supplied by the multiplexer corresponds to the specific sync word. Additional RAMs (62, 76, 78) are used as counter decoders to define word bit length, frame word length, and paragraph frame length.