Abstract: A digital desynchronizer (10) includes an elastic store unit (12) that receives a synchronously mapped asynchronous data signal (14) and outputs asynchronous output data over an asynchronous output data signal (20) in response to an output clock signal (22). The output clock signal (22) is generated by a digitally controlled oscillator (24). The digitally controlled oscillator (24) receives a speed up signal (28) and a slow down signal (30) from a jitter accumulator (26) in order to adjust the clock rate of the output clock signal (22). The jitter accumulator (26) compares retimed read address information (32) to write address information (34) from the elastic store unit (12), subtracts an initial bias, adds the result to any previous sum, and compares this final result to programmable threshold levels in order to determine whether or not to assert the speed up signal (28) or the slow down signal (30).