Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.

Abstract: A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.

Abstract: A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.

Abstract: A sparse-carrier device comprising a crystal structure formed of a first material and including a crystallographic facet having a length, a first width and a second width, and quantum dots formed of a second material and positioned on the crystallographic facet, the quantum dots extending along the length of the crystallographic facet in a first distribution pattern along the first width and a second distribution pattern along the second width.

Abstract: A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.

Abstract: A method of removing an oxide mask during fabrication of semiconductor devices which includes providing a providing a III-V compound semiconductor substrate having a surface, the surface having a growth area and a masked area masked by an oxide film formed on the surface thereof. The oxide film is removed with a Trisdimethylamino group V compound.

Abstract: A method of fabricating semiconductor devices including forming a plurality of layers of semiconductor material on the surface of a substrate, forming a mask without using a resist on the layers which can be disassociated in-situ, removing an unmasked portion of the layers to form a semiconductor device with a gate region and opposed exposed source and drain surfaces, selectively growing source and drain contact regions on the exposed source and drain surfaces respectively, the contact regions defining opposed sidewalls adjacent the gate region, disassociating the mask, forming sidewall spacers on the sidewalls, forming a metal contact on the source, drain and gate regions with the spacers preventing intercontact therebetween, and depositing a passivating layer over the semiconductor device, with all of the previous steps being performed in-situ in a modular equipment cluster.

Abstract: A heterojunction tunnel diode with first and second barrier layers, the first barrier layer including aluminum antimonide arsenide. A quantum well formation is sandwiched between the first and second barrier layers, and includes first and second quantum well layers with a barrier layer sandwiched therebetween, the first quantum well layer being adjacent the first barrier layer. The first quantum well layer is gallium antimonide arsenide which produces a peak in hole accumulations therein. The second quantum well layer produces a peak in electron accumulations therein. A monolayer of gallium antimonide is sandwiched in the first quantum well layer at the peak in hole accumulations and a monolayer of indium arsenide is sandwiched in the second quantum well layer at the peak in electron accumulations.

Abstract: Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

Abstract: A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.

Abstract: The present invention is a method of forming a quantum multi-function semiconductor device. In the method of the present invention, an insulating layer (12) is formed on a semiconductor substrate (11). An opening (14) is formed in the insulating layer (12), and a channel region (15) is formed in the opening (14). A channel layer (21) is formed over the channel region (15). An opening (23) is formed through the channel layer (21) such that a portion of the opening is over a portion of the channel region (15). A source electrode (28) is formed to contact a channel layer (17) of the channel region (15), a drain electrode (29) is formed to contact the channel layer (21), and a gate electrode (31) is formed to contact the second barrier layer (27).

Abstract: A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.

Abstract: A GaAs heterostructure is formed with a GaAs.sub.y P.sub.1-y stress-compensating layer. The heterostructure is comprised of a GaAs substrate and GaAs.sub.y P.sub.1-y stress-compensating layer formed on the GaAs substrate. The stress-compensating layer has a lattice constant less than the lattice constant of the GaAs substrate. A channel layer formed on the stress-compensating layer, has a lattice constant greater than the lattice constant of the GaAs substrate. Thus, a pseudomorphic heterostructure may be formed, with the optimum thickness and doping in the channel layer to provide for improved electrical characteristics.

Abstract: A heterojunction bipolar transistor (HBT) is provided having a silicon substrate in which a conventional junction base is formed. A coherently strained layer of semiconductor material having a wider band gap than silicon, such as gallium phosphide, is formed over the base to form a first portion of an emitter multilayer. A second portion of the emitter multilayer comprises silicon which can be epitaxially grown on the coherently strained layer. A thin heteropotential barrier is thus formed at the base-emitter junction which preferentially allows electrons to move from emitter to base while significantly reducing hole current from base to emitter, thereby improving emitter injection efficiency and current gain.