Abstract: A resistorless amplifier circuit uses integrated operational transconductance amplifiers to realize a plurality of circuit transfer functions. The preferred embodiment produces an output signal voltage V.sub.out (500) that is either g.sub.m1 /g.sub.m3 or g.sub.m1 /(g.sub.m3 -g.sub.m1) times the input signal voltage V.sub.in (400). Additionally, an alternative embodiment implements a resistorless summing and subtracting operational transconductance amplifier circuit that realizes an output signal voltage as follows: ##EQU1## The resistorless amplifier circuit includes a first operational transconductance amplifier (100) with a transconductance g.sub.m1, a second operational transconductance amplifier (200) with a transconductance g.sub.m2, and a third operational transconductance amplifier (300) with a transconductance g.sub.m3.

Abstract: A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).

Abstract: A current mirror (100) has an input stage (104) and an output stage (106), both preferably employing FET's. (Field Effect Transistors) An amplifier (102) equalizes drain-to-source voltages between FET's in the input and output stages to provide a higher output impedance. A resistance (R1), coupled in series with an FET in the output stage (106), provides degenerative feedback. A reference current generator (400) is constructed of two such current mirrors, one being the compliment of the other, to provide one or more stable reference currents. Loop gain of the reference current generator (400) is greater than one at start-up, but degenerative feedback reduces the loop gain to one at a predetermined stable operating point.

Abstract: An oscillator circuit (143) comprises a master phase-locked loop (PLL) circuit (202) that receives as input a first reference frequency signal (136) and generates a first clock signal (210) in response to an oscillator control signal (212). The oscillator circuit (143) includes a frequency sensitive slave circuit (206) having at least one frequency sensitive element (322) that is responsive to a tracking control signal (214) to generate a second clock signal (216). A tracking control circuit (204) is responsive to the oscillator control signal (212) for generating the tracking control signal (214). The tracking control signal (214) serves as a bias signal, and is connected to the frequency sensitive slave circuit (206) for achieving a fast power up sequence of the oscillator circuit (143).

Abstract: A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

Abstract: A current controlled variable frequency oscillator (260) operates at a characteristic frequency that is determined primarily by a scaled current. A filter cascade (320) receives the scaled current for setting a filter cascade frequency substantially equal to the characteristic frequency. Additionally, the filter cascade (320) receives a triangular signal at a non-inverting input, the filter cascade (320) converting the triangular signal into a sinewave signal. A lowpass filter (330) receives the scaled current for setting a lowpass filter frequency to a frequency substantially less than the characteristic frequency. The lowpass filter (330) also receives the sinewave signal and provides an average signal therefrom. A comparator (340) receives the scaled current, wherein the comparator (340) compares the sinewave signal and the average signal for providing a substantially squarewave signal therefrom.

Abstract: A display system (500) processes an input signal to generate an image. The input signal includes successive frames of data defining lines which include image values and have a line direction. A display (100) for displaying the image has second electrodes (104) which are in a direction corresponding to the line direction. A video memory (640) which stores a frame of data includes a single line buffer (602) and a single frame buffer (608). A controller (622) controls storage of the frame of data into the video memory (640) and generates a predetermined image independent function during a time slot. A calculation engine (632) computes an image dependent output signal during the time slot which has values. Each of the values is determined from the predetermined image independent function and image values from one of the lines stored in the video memory (640).

Abstract: A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.

Abstract: A voltage track and hold circuit operates to track a tuning voltage and holding the tuning voltage (404) as a reference voltage (408). In the track mode, the track and hold circuit includes a first operational transconductance amplifier (401) and a first charge storage device (402) coupled to a first input (403) of the first operational transconductance amplifier (401). The first charge storage device (402) accumulates a charge that corresponds with the tuning voltage (404). A second charge storage device (405) is coupled to a second input (406) and an output (407) of the first operational transconductance amplifier (401). The second charge storage device (405) accumulates a reference charge such that the reference voltage (408) present at the second charge storage device (405) is substantially equivalent to the tuning voltage (404).

Abstract: A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.

Abstract: A complementary cascode push-pull amplifier circuit includes a bias generator, a complementary bias generator, a cascode input stage (416, 417), a cascode output stage (410, 411), a complementary cascode input stage (456,457), and a complementary cascode output stage (450,451). The bias generator is responsive to a first input signal (420) and generates a bias control voltage. The complementary bias generator is responsive to a second input (421) and generates a complementary bias control voltage. The cascode output stage (410, 411) and the complementary cascode output stage (450,451) each have an output coupled to a common output terminal (510) for generating a portion of an output current signal in response to the respective input signals (420, 421) and in response to the bias control voltage and the complementary bias control voltage being generated.

Abstract: A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.

Abstract: An operational transconductance amplifier (38) is coupled to first and second supply voltages (41, 42) for converting differential input signals into a proportional output current. The operational transconductance amplifier (38) has a predetermined common mode input range, and a differential amplifier input stage (28, 29) having a non-inverting input (Vin+), and an inverting input (Vin-). The non-inverting and inverting inputs (Vin+, Vin-) receives differential input signals. Parallel connected transistors (36, 37) are coupled to the differential amplifier input stage (28, 29) for receiving the differential input signals. A current mirror (20-23) has first and second current paths, wherein the first current path sinks a common mode current from the differential amplifier stage, and wherein the second current path diverts the common mode current from the differential amplifier input stage (28, 29) in the event that the differential input signals fall below a predetermined magnitude.

Abstract: A class AB transconductance amplifier (200) has first and second differential input amplifier stages (100-112) adapted for receiving first and second differential input signals (Vin+, Vin-). First and second input cascode stages are coupled to the first and second differential input amplifier stages for providing first and second differential folded cascode signals. An output stage (113-118) is coupled to the first and second differential folded cascode signals providing an output signal indicative of a difference between the first and second differential input signals (Vin+, Vin-). A bias stage (101, 102) is coupled to said first and second differential input amplifier stages (103-104, 105-106) and the first and second input cascode stages bias the first and second differential input amplifier stages (100-112) to operate as a class AB folded cascode amplifier circuit (200). The bias stage generates class AB biasing signals.

Abstract: A coil assembly that is essentially isotropic in a plane normal to the plane of the coil includes two flat coils stacked one next to the other. One coil is connected in series with a resistor in a closed loop and has a strip of high permeability material woven through it. The other coil is tuned by a parallel capacitor across its coil terminals, such terminals being connected to electronic circuitry. The coil is separated from the printed circuit board that contains the electronic circuitry by a sheet of high permeability material. The assembly is self-contained and powered by a flat battery on which the circuit board is placed. Another embodiment is disclosed that contains only one coil, the terminals of which are connected to a suitable electronic circuit, not shown. Strips of high permeability material are disposed on both sides of the coil and an assembly is produced with a printed circuit board and a flat battery.

Abstract: A coil assembly that is essentially isotropic in a plane normal to the plane of the coil includes two flat coils stacked one next to the other. One coil is connected in series with a resistor in a closed loop and has a strip of high permeability material woven through it. The other coil is tuned by a parallel capacitor across its coil terminals, such terminals being connected to electronic circuity. The coil is separated from the printed circuit board that contains the electronic circuitry by a sheet of high permeability material. The assembly is self-contained and powered by a flat battery on which the circuit board is placed. Another embodiment is disclosed that contains only one coil, the terminals of which are connected to a suitable electronic circuit, not shown. Strips of high permeability material are disposed on both sides of the coil and an assembly is produced with a printed circuit board and a flat battery.

Abstract: A duplexer is provided in which a transmit input signal is fed in parallel through two autotransformers to a pair of portal loops for establishing an interrogation field. Significantly lower voltage response signals returning via the autotransformers are applied in push-push relationship to the primary of one transformer for producing a difference signal output, and in parallel to a second transformer primary for producing a sum signal output. Back-to-back diodes across the secondary windings of the sum and difference output transformers limit the volt drop across the respective primaries for the relatively higher voltage transmit input signal. The response signal, however, is below the threshold of the diodes and, consequently, the diodes do not attenuate such signal.

Abstract: Communication between portal units and identification tags is accomplished by continually radiating an interrogation signal consisting of a code pattern from each portal unit followed by a listening interval. Tags within range of such interrogation signal test the incoming signals for frequency, bit duration, bit rate, a preamble code and a facility identifying code. If the tag receives a valid signal to which it has been preprogramed, such signal synchronizes and initiates a plurality of tag responses within a given overall response interval and with each response transmitted during randomly selected time slot. Each tag is provided with its own pseudorandom binary sequence generator and reply counter with the pseudorandom generator sequenced by a signal derived from the carrier signal radiated by the tag.The portal units also test incoming signals for frequency bit rate and bit duration as well as for a preamble code generically indicative of a tag.