Abstract: A monolithic integrated circuit comprises a substrate having first and second opposing major surfaces. A semiconductor device is at the first major surface, a circuit film pattern is on the second major surface, and means for interconnecting the device to the film pattern are provided. On the first surface, a metallization layer surrounds the device and has a thickness greater than the height of the device from the first surface. Additionally, an electrode extension projects from the device to a height substantially equal to the thickness of the metallization layer.

Abstract: First and second field effect transistors (FETs) each have a gallium arsenide substrate with an N-type active region that carries first and second electrodes in ohmic contact therewith and a gate electrode. The FETs are mounted in a flip-chip carrier that connects the first electrodes to ground. The FETs are biased to cause a current to flow from the first to second electrodes, whereby the first and second electrodes serve as drains and sources, respectively, of the FETs. The gate of the first FET is connected to a resonator. Additionally, a matching network connects the source of the first FET to the gate of the second FET. The matching network and the biasing of the first FET cause the gate input impedance thereof to be of a negative value that compensates for losses in the resonator. A load connected to the source of the second FET and the bias voltage cause the second FET to have a gate input impedance of a negative value that causes oscillation.