Abstract: Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests.

Abstract: Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests.

Abstract: Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a packet, the packet may be unloaded from the first and second buffer while a new packet is simultaneously loaded to the packet header processing engine.

Abstract: A system for multicasting a packet of data to a single data stream is provided. The system may determine a size of the packet and may send a single copy of the packet if the size of the packet exceeds a threshold value. A number of copies of the packet yet to be multicast may be ascertained if the size of the packet of data does not exceed the threshold value. Copies of the packet may be transmitted based on the number of copies of the packet yet to be multicast.

Abstract: A network device includes a memory and a packet forwarding engine. The memory stores a multicast list table, tag descriptor data and layer 2 (L2) encapsulation data. The packet forwarding engine receives a first pointer to an entry in the multicast list table, the entry including a second pointer to the tag descriptor data. The packet forwarding engine utilizes the second pointer to retrieve the tag descriptor data, the tag descriptor data including a third pointer to the encapsulation data. The packet forwarding engine constructs a packet header utilizing the retrieved encapsulation data and appends the packet header to a packet payload for forwarding out of the packet forwarding engine.

Abstract: A processing engine for processing header data includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a data unit, the data unit may be unloaded from the first and second buffer while a new data unit is simultaneously loaded to the header processing engine.

Abstract: A packet header processing engine receives a header of a packet. The received header includes a size of the packet. A maximum transfer unit size of a destination interface of the packet may be determined. The packet header processing engine determines whether the size of the packet exceeds the maximum transfer unit size of the destination interface. If the size of the packet does not exceed the maximum transfer unit size of the destination interface, the packet header processing engine generates a new header from the received header. If the size of the packet exceeds the maximum transfer unit size of the destination interface, the packet header processing engine generates a fragment header from the received header. The packet header processing engine may recycle the fragment header for further processing in addition to forming a first fragment packet from the fragment header.

Abstract: A network device includes a memory and a packet forwarding engine. The memory stores a multicast list table, tag descriptor data and layer 2 (L2) encapsulation data. The packet forwarding engine receives a first pointer to an entry in the multicast list table, the entry including a second pointer to the tag descriptor data. The packet forwarding engine utilizes the second pointer to retrieve the tag descriptor data, the tag descriptor data including a third pointer to the encapsulation data. The packet forwarding engine constructs a packet header utilizing the retrieved encapsulation data and appends the packet header to a packet payload for forwarding out of the packet forwarding engine.

Abstract: A system for multicasting a packet of data to a single data stream is provided. The system may determine a size of the packet and may send a single copy of the packet if the size of the packet exceeds a threshold value. A number of copies of the packet yet to be multicast may be ascertained if the size of the packet of data does not exceed the threshold value. Copies of the packet may be transmitted based on the number of copies of the packet yet to be multicast.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution section and the L3 generation unit may include multiple parallel execution sections. When both the L2 and L3 generation units complete their operations on a particular packet, a build component combines the generated L2 and L3 information to form a complete packet header.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a packet, the packet may be unloaded from the first and second buffer while a new packet is simultaneously loaded to the packet header processing engine.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. Mailbox registers allow the L2 and L3 header generation units to communicate with one another. The L2 header generation unit may write to a specified mailbox register only when a valid bit corresponding to the mailbox register indicates that the register does not contain valid data. After writing to the mailbox register, the L2 header generation unit changes the state of the valid bit. The L3 register then reads from the mailbox register and changes the state of the valid bit. A similar implementation of the mailbox registers allows data to flow from the L3 header generation unit to the L2 header generation unit.

Abstract: A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.