Patents by Inventor Raymond M. Sicina

Raymond M. Sicina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7859060
    Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Jakub Kedzierski, Raymond M. Sicina
  • Patent number: 7816224
    Abstract: In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Jakub Kedzierski, Raymond M. Sicina
  • Publication number: 20090289303
    Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
    Type: Application
    Filed: August 4, 2009
    Publication date: November 26, 2009
    Inventors: KEVIN K CHAN, Jakub Kedzierski, Raymond M. Sicina
  • Publication number: 20090224320
    Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 10, 2009
    Inventors: KEVIN K. CHAN, Jakub Kedzierski, Raymond M. Sicina
  • Patent number: 6350321
    Abstract: A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: February 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Christopher P. D'Emic, Raymond M. Sicina, Paul M. Kozlowski, Margaret Manny, Sandip Tiwari