Abstract: A system and method for parallel-beam scanning a surface. An energetic beam source emits an energetic collimated beam which is received by an optical device, comprising: one or more optical media, operable to receive the emitted beam, such as two pairs of coordinated mirrors or a right prism, and at least one actuator coupled to the one or more optical media, and operable to rotate each of the one or more optical media around a respective axis to perform a parallel displacement of the beam in a respective direction, wherein the respective direction, the beam, and the respective axis are mutually orthogonal. The optical device is operable to direct the beam to illuminate a sequence of specified regions of a surface.

Abstract: A system and method for parallel-beam scanning a surface. An energetic beam source emits an energetic collimated beam which is received by an optical device, comprising: one or more optical media, operable to receive the emitted beam, such as two pairs of coordinated mirrors or a right prism, and at least one actuator coupled to the one or more optical media, and operable to rotate each of the one or more optical media around a respective axis to perform a parallel displacement of the beam in a respective direction, wherein the respective direction, the beam, and the respective axis are mutually orthogonal. The optical device is operable to direct the beam to illuminate a sequence of specified regions of a surface.

Abstract: Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterned beam of energetic radiation; and (3) flash diffusion focuses through a projector barrel the patterned beam on a silicon sample, causing localized dopant diffusion from a heavily doped region at the surface into the underlying region. Removing the heavily doped layer leaves a 2-D doping pattern. Creating additional 2-D patterns on top of it through process repetition produces a buried 3-D doping pattern. One configuration places projector barrel and sample in fixed positions inside the sputtering chamber and a ring of targets around the barrel facing the sample with targets of a given kind symmetrically positioned in the ring. Cobalt can be substituted for the doping layer and can be driven in creating silicide conductive patterns.

Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.

Abstract: A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated circuit (IC). The crystal is grown as a large number of lightly-doped layers in a single-pumpdown procedure using sputter epitaxy, which offers growth rates for good-quality silicon of at least 0.1 micrometer per minute. The process experiences a stable environment with temperature remaining around 400 C and pressure near 1 millitorr, and the process is "quasicontinuous" in that once each layer is in place, its surface will experience a short series of further steps that create a 2-D doping pattern extending through the layer. It is the merging of many such successive 2-D patterns that creates the desired 3-D doping pattern within the finished silicon crystal.

Abstract: A digital logic circuit having multiple inputs and a product-of-sums output uses multi input OR circuits with interacting constant-current and constant-voltage elements to improve voltage transfer characteristics. A second-level arbitration circuit connects to the OR circuits and provides mutually exclusive pull-up and pull-down control signals as a logical function of the states of the OR circuits. An output stage connects to the arbitration circuit. The output stage comprises pull-up and pull-down drivers responsive to the output of the second-level arbitration circuit. The digital logic circuit operates at high speed because its transistors are prevented from entering saturation. The logic circuit is easily expandable and provides a simple and direct method of implementing logic circuits which provide product-of-sums outputs.

Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.

Abstract: A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+ - P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy. Also, a thin layer of silicide can be provided as an ohmic contact and/or a thick layer of silicide can be provided as a conductor thereby providing monocrystalline 3-D devices or integrated circuits. Finally, an insulator can be provided about an entire device for isolation.

Abstract: A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications.

Abstract: A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+-P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy.

Abstract: A thin film magnetic recording playback head is disclosed wherein mechanically coupled films of a magnetostrictive material and of a piezoresistive material are utilized with a solid state amplifier electrically coupled to sense resistance changes in the piezoresistive film. In operation, localized magnetic patterns on a recording medium induce strain in the magnetostrictive film, which in turn induces in the piezoresistive film corresponding changes in electrical resistance.

Abstract: A photovoltaic semiconductor device which is a horizontal multijunction series-array solar battery with a monocrystalline body and having elongate zones of aluminum doped silicon passed entirely through N-type silicon layers by Thermomigration process to connect together epitaxially grown buried P layers. Masked elongate N diffusion zones which are parallel and substantially contiguous to each elongated P zone penetrates at least through the lowest P layer thereby forming an inactive pn junction. A thin shallow layer of P-type material is diffused across the top N-type layer. Topologically continuous photovoltaic junctions exist in each cell of the photovoltaic semiconductor device between the shallow layer of P-type material, the buried layer or layers of P-type material, the elongate zone of aluminum doped silicon, and the N-type silicon thereby forming active pn junctions.

Abstract: Apparatus and method for constructing by means of standard high-yield microelectronic batch fabrication processes, reliable, monolithic high-voltage photovoltaic cells and highly efficient photovoltaic arrays therewith. A thin layer of single-crystalline semiconductor material containing a plurality of sublayers defining one or more active junctions in planes parallel to an upper irradiated surface thereof, overlies a supportive insulating substrate body. Widely spaced pairs of elongate heavily doped zones of opposite conductivity types produced by two short diffusion steps extend into the thin layer, defining photovoltaic cells therebetween and providing low-impedance conductive paths for photovoltaic carriers generated in the thin layer to the upper irradiated surface. By overlapping opposite-conductivity pairs of the heavily doped elongate zones, simultaneous dielectric isolation and series connection of adjacent cells is achieved.