Abstract: An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

Abstract: An oscillator comprises a comparator and first and second switches for alternately connecting first and second respective reference voltages to a first input of the comparator. A capacitor is connected to a second input of the comparator, and a current source and a current sink are alternately connected to the capacitor via third and fourth switches. The first and third switches are closed simultaneously based on one output level of the comparator, and the second and fourth switches are closed simultaneously based on the other output level of the comparator. This causes the output of the compartor to alternate and thereby generate an oscillation signal. To provide precision in the duty cycles, either the second reference voltage, the current source or the current sink is adjusted to maintain desired duty cycles of the high and low levels output from the comparator.

Abstract: A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.

Abstract: A differential transimpedance amplifier used in amplifying optical signals transmitted with a balanced code has a level restore circuit which integrates the digital output of the amplifier and feeds back the result to one of the differential inputs of the amplifier. The feedback signal removes imbalances from the amplifier output. The balanced amplifier output can then be processed by a clock reconstruction circuit to accurately sample the received optical signal with a low bit error rate.

Abstract: An amplifier circuit comprises first and second gain cells connected in cascade. Each of the gain cells comprises first and second common emitter differential transistors, a current source coupled to the emitters of the transistors, a first plurality of forward biased, series diodes connected between a power supply terminal and a base of the first transistor, and a second plurality of forward biased, series diodes connected between the power supply terminal and a base of the second transistor. A collector of the first transistor of the first gain cell is connected to the base of the first transistor of the second gain cell, and a collector of the second transistor of a first gain cell is connected to the base of the second transistor of the second gain cell. Because of the low inherent resistance of the biasing diodes, the operating speed of the amplifier is large, and the current amplification can be large without exceeding the power supply voltage.

Abstract: Monitor circuitry is placed in the closed loop of a phase-locked loop (PLL) circuit and is capable of detecting the existence of an out of frequency window condition and outputting a control signal when the PLL is operating outside the predetermined narrow frequency window. Recovery circuitry, including a phase frequency detector with a wide acquisition range, temporarily replaces the normal phase detector of the PLL, responsive to the control signal from the monitor circuitry. When the monitor circuitry determines that the PLL is back within the predetermined narrow frequency window, the PLL phase detector is switched back into the PLL loop and the phase frequency detector is removed from the PLL loop. The PLL phase detector is then able to lock in on the incoming data stream.