Abstract: A method for modeling metastablilty decay in digital circuit devices includes identifying each latch at a receiving end of an asynchronous clock boundary, enumerating a latch depth for each latch within logical influence of each of the identified receive latches, and inserting fence logic immediately prior to the input of each latch at an enumerated depth, n, wherein n represents a latch depth at which an indeterminate metastable value received at the asynchronous boundary decays to a random logic value. The fence logic converts an identified indeterminate value to a random logic value, and any indeterminate value initially received is allowed to propagate up to the fence logic.

Abstract: A method, apparatus and computer program product are provided for facilitating combinatorial logic modeling at an asynchronous clock domain crossing. The modeling technique employs a simulation value of X in combinatorial logic at the asynchronous clock domain crossing of a circuit being modeled to facilitate modeling of a potential combinatorial logic glitch at the crossing during metastability periods thereof. Employing the simulation value of X includes: generating one or more equivalent functional equations for one or more combinatorial paths through the combinatorial logic at the crossing; propagating the simulation value of X through the combinatorial logic using the at least one equivalent functional equation; and then converting the simulation value of X at an output of the combinatorial logic of the asynchronous clock domain crossing to a random logic value for further propagation within the circuit being modeled.

Abstract: A method, apparatus and computer program product are provided for implementing RTL power sequencing simulation of voltage islands for application specific integrated circuit (ASIC) designs. RTL sequential state saving elements in a voltage island hierarchy are identified. A state is invalidated for each identified RTL sequential state saving element during a power down operation. Switch objects are used to identify and skip globally powered gate level circuits in the voltage island. RTL sequential state saving elements and VI switch objects can be identified using predefined reserved signal identifiers in the ASIC library.

Abstract: A method, module, and program product for detecting signal strengths in a hardware description language, such as Verilog, that does not provide for such detection. The method includes the steps of creating a wired net configuration that provides for a data input signal and a controlled reference signal; varying the controlled reference signal based on a desired signal strength to be detected; and comparing the input signal with the controlled reference signal to determine if the desired signal strength has been detected.

Abstract: Dynamic cosimulation is implemented using a cosimulation bridge for data exchange between a primary simulator and a secondary simulator, and a plurality of user selected optimization control signals defined over the cosimulation bridge. At least one user selected optimization control signal is identified for disabling the cosimulation bridge. The primary simulator and secondary simulator are dynamically disengaged for ending data exchange responsive to disabling the cosimulation bridge. Responsive to optimization control signal going inactive, the primary simulator and secondary simulator are dynamically re-engaged for data exchange. The optimization control signals include a single sided disable; a two independent disable; a functional OR disable; a functional AND disable, and suspend signals. The single sided disable and the two independent disable enable disabling one side of the cosimulation bridge and not the other side.