Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrodes. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the internal electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups. Each exposed portion is within a predetermined distance from other exposed portions in a given group such that termination structures may be formed by deposition and controlled bridging of a thin-film plated material among selected of the exposed internal conductive elements. Electrolytic plating may be employed in conjunction with optional cleaning and annealing steps to form directly plated portions of copper, nickel or other conductive material. Once an initial thin-film metal is directly plated to a component periphery, additional portions of different materials may be plated thereon.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of first and second polarity electrode layers. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups and thin-film plated deposition is formed thereon by electroless and/or electrolytic plating techniques. A solder dam layer is provided over a given component surface and formed to expose predetermined areas where solder barrier and flash materials may be deposited before attaching solder preforms. Some embodiments include plated terminations substantially covering selected component surfaces to facilitate with heat dissipation and signal isolation for the electronic components.

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract: A method for forming a copper-Invar-copper (CIC) laminate having an intermetallic layer of negligible thickness, and a structure associated with the CIC laminate. Starting with a block of Invar, the method includes a cleaning step followed by an electroplating step. The cleaning step electrochemically cleans the block of Invar with an acid solution while applying a negative voltage bias to the block of Invar. The electroplating step electroplates copper on the block of Invar, resulting in the block of Invar being sandwiched between two layers of copper, such that an intermetallic layer of zero or negligible thickness is disposed between the block of Invar and each layer of copper. Each layer of copper has a uniform thickness. If the starting block of Invar contains a through hole, then the electroplating step will plate a ring of copper on the through hole wall.

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract: A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract: A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Abstract: An arrangement and method for the degassing small high-aspect ratio drilled holes or vias which are present in panels such as printed circuit boards prior to wet chemical processing, including copper plating of the vias, in order to remove any air or gas bubbles from the vias tending to inhibit the reliable plating thereof. This is carried out through the utilization of an ultrasonic prewetting in a liquid bath preceding cleaning for the electroless plating process, thereby enabling all of the vias or holes to be degassed; in effect, having air removed and the vias or holes filled with liquid; thereby allowing subsequent process cleansing solutions to easily flow into the respective holes or vias in order to facilitate the electroless copper plating process.

Abstract: An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer includes a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: A method for forming a copper-Invar-copper (CIC) laminate having an intermetallic layer of negligible thickness, and a structure associated with the CIC laminate. Starting with a block of Invar, the method includes a cleaning step followed by an electroplating step. The cleaning step electrochemically cleans the block of Invar with an acid solution while applying a negative voltage bias to the block of Invar. The electroplating step electroplates copper on the block of Invar, resulting in the block of Invar being sandwiched between two layers of copper, such that an intermetallic layer of zero or negligible thickness is disposed between the block of Invar and each layer of copper. Each layer of copper has a uniform thickness. If the starting block of Invar contains a through hole, then the electroplating step will plate a ring of copper on the through hole wall.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: An electronic structure that includes a copper-Invar-copper (CIC) laminate of negligible thickness, such as a thickness not exceeding about 0.5 microns. The electronic structure may have a via passes through the CIC laminate such that the via is plated with a ring of copper. The ring of copper and the copper in the CIC laminate may have about the same grain structure.

Abstract: An arrangement and method for the degassing small high-aspect ratio drilled holes or vias which are present in panels such as printed circuit boards prior to wet chemical processing, including copper plating of the vias, in order to remove any air or gas bubbles from the vias tending to inhibit the reliable plating thereof This is carried out through the utilization of an ultrasonic prewetting in a liquid bath preceding cleaning for the electroless plating process, thereby enabling all of the vias or holes to be degassed; in effect, having air removed and the vias or holes filled with liquid; thereby allowing subsequent process cleansing solutions to easily flow into the respective holes or vias in order to facilitate the electroless copper plating process.

Abstract: A method of removing a metal skin from a through-hole surface of a copper-Invar-copper (CIC) laminate without causing differential etchback of the laminate. The metal skin includes debris deposited on the through-hole surface as the through hole is being formed by laser or mechanical drilling of a substrate that includes the laminate as an inner plane. Removing the metal skin combines electrochemical polishing (ECP) with ultrasonics. ECP dissolves the metal skin in an acid solution, while ultrasonics agitates and circulates the acid solution to sweep the metal skin out of the through hole. ECP is activated when a pulse power supply is turned on and generates a periodic voltage pulse from a pulse power supply whose positive terminal is coupled to the laminate and whose negative terminal is coupled to a conductive cathode. After the metal skin is removed, the laminate is differentially etched such that the copper is etched at a faster rate than the Invar.

Abstract: The present invention relates to a method for selectively electroetching a metal from an electrical device having the steps of: immersing the electrical device in an etching solution; immersing a cathode in the etching solution; applying an etching potential to a preselected area of the metal; and maintaining a passivation potential at the metal to remain unetched. The metal to remain unetched is not electrically connected to the preselected area and the passivation potential does not equal the etching potential.The present invention further relates to a method of forming an electrical connection to the inner layers of a multilayer circuit board having a copper foil surface layer and copper containing inner layers.

Abstract: Disclosed is a method of laminating circuitized polymeric dielectric panels with pad to pad electrical connection between the panels. This pad to pad electrical connection is provided by a transient liquid phase formed bond of a joining metallurgy characterized by a non-eutectic stoichiometry composition of a eutectic forming system. The eutectic temperature of the system is below the first thermal transition of the polymeric dielectric, and the melting temperature of the joining metallurgy composition is above the first thermal transition temperature of the polymeric dielectric.