Patents by Inventor Raymond Tak-Hoi LEUNG

Raymond Tak-Hoi LEUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Negative bias thermal instability stress testing of transistors
    Patent number: 9857409
    Abstract: A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: January 2, 2018
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Tak-Hoi Leung
  • Evaluation of thermal instability stress testing
    Patent number: 9817059
    Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 14, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Jamil Kawa, Thu Nguyen, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Tak-Hoi Leung
  • Circuit skew compensation trigger system
    Patent number: 9742406
    Abstract: A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: August 22, 2017
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Thu Nguyen, Raymond Tak-Hoi Leung
  • Dynamic static random access memory (SRAM) array characterization using an isolated bit-line
    Patent number: 9424951
    Abstract: A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 23, 2016
    Assignee: Synopsys, Inc.
    Inventors: Raymond Tak-Hoi Leung, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Jamil Kawa
  • EVALUATION OF THERMAL INSTABILITY STRESS TESTING
    Publication number: 20150369855
    Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 24, 2015
    Applicant: SYNOPSYS, INC.
    Inventors: Jamil Kawa, Thu Nguyen, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Tak-Hoi Leung
  • CIRCUIT SKEW COMPENSATION TRIGGER SYSTEM
    Publication number: 20150365075
    Abstract: A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.
    Type: Application
    Filed: June 11, 2015
    Publication date: December 17, 2015
    Inventors: Jamil Kawa, Thu Nguyen, Raymond Tak-Hoi Leung
  • NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING OF TRANSISTORS
    Publication number: 20150061726
    Abstract: A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor.
    Type: Application
    Filed: August 15, 2014
    Publication date: March 5, 2015
    Inventors: Jamil KAWA, Tzong-Kwang Henry YEH, Shih-Yao Christine SUN, Raymond Tak-Hoi LEUNG
  • DYNAMIC STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY CHARACTERIZATION
    Publication number: 20150063009
    Abstract: A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.
    Type: Application
    Filed: August 15, 2014
    Publication date: March 5, 2015
    Inventors: Raymond Tak-Hoi LEUNG, Tzong-Kwang Henry YEH, Shih-Yao Christine SUN, Jamil KAWA
  • NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)
    Publication number: 20150063010
    Abstract: In one embodiment, one portion of an SRAM array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the SRAM. The other portion of the array is then stressed after writing a “0” in every bit of the array. The evaluation procedure is then repeated.
    Type: Application
    Filed: August 15, 2014
    Publication date: March 5, 2015
    Inventors: Jamil KAWA, Tzong-Kwang Henry YEH, Shih-Yao Christine SUN, Raymond Tak-Hoi LEUNG