Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.

Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.

Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information. For example, it may be determined at a requesting agent processor that IO traffic is to be received at the target processor cache, wherein the target processor is different than the requesting agent processor. Moreover, routing information associated with the IO traffic may be received from the requesting agent processor. It may then be arranged for the IO traffic to be transferred directly into the target processor cache in accordance with the routine information.

Abstract: Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises receiving a message signaled interrupt, parsing an interrupt vector from the message signaled interrupt, locating an interrupt entry associated with the interrupt vector in a table of interrupt entries, and sending information associated with the interrupt entry to a processor.

Abstract: An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

Abstract: Methods and apparatuses for reserving an execution thread are disclosed. A selected processing unit is described as a peripheral device in a device description. Peripheral devices are prevented from using the selected processing unit. A processor description includes one or more available processing units, and omits the selected processing unit. The processor description is provided to an operating system. The device description of the selected processing unit may be read and recognized as a device description of a peripheral device. A device driver may be retrieved for the processing units based on the device description of the processing unit, and resources may be allocated to the processing unit based on a request from the driver.

Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.

Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.