Patents by Inventor Raymond Thomas Galasco

Raymond Thomas Galasco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7378227
    Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
  • Patent number: 6815126
    Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
  • Publication number: 20030188886
    Abstract: A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.
    Type: Application
    Filed: April 9, 2002
    Publication date: October 9, 2003
    Applicant: International Business Machines Corporation
    Inventors: Edmond Otto Fey, Raymond Thomas Galasco, Thomas Richard Miller, Anita Sargent
  • Patent number: 6179990
    Abstract: A method for cleaning a copper-INVAR-copper laminate in an acid solution without inducing a galvanic etching of the INVAR. An initial step of the method forms a circuit element that includes a power supply, the laminate electrically coupled to a negative terminal of the power supply, and a conductive anode electrically coupled to a positive terminal of the power supply. The conductive anode may include a conductive material, such as titanium, that is preferably inert to an acid solution into which the laminate will be subsequently immersed. After turning on the power supply to a voltage between about 1 volts and about 10 volts, the laminate and conductive anode are immersed in the acid solution, so as to form a closed circuit with a voltage bias across acid copper-INVAR-copper interfaces. The voltage bias prevents galvanic action from occurring and therefore protects against galvanic etching of the INVAR.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Raymond Thomas Galasco, Lawrence Philip Lehman, Roy Harvey Magnuson, Robert David Topa
  • Patent number: 6176985
    Abstract: An electroplating apparatus provides high current electrical connections in a small area to a workpiece. The contact area may use a dendrite surface to improve the connection. An insulative gasket prevents electroplating fluids from entering the region about the contact area. A heavy core laminated within a supporting structure provides uniform current distribution of high electrical currents to the dendrite covered contact areas.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: January 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Francis J. Downes, Jr., Raymond Thomas Galasco, Robert Maynard Japp, John Frank Surowka
  • Patent number: 6043150
    Abstract: The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The method comprises the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventors: Francis Joseph Downes, Jr., Raymond Thomas Galasco, Jaynal Abedin Molla
  • Patent number: 5939786
    Abstract: The present invention provides uniform dendrites, on circuit features instead of large, elongated dendrites along the edges of the circuit features. The dendrites are formed by a method comprising the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: August 17, 1999
    Assignee: International Business Machines Corporation
    Inventors: Francis Joseph Downes, Jr., Raymond Thomas Galasco, Jaynal Abedin Molla