Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: A nonvolatile memory device comprising first and second transistors connected between respective first and second terminals and a reference potential terminal, the transistors having first and second floating gates, respectively, for storing complementary charges. The device further comprises first and second input lines capacitively coupled to the gates, and means for providing a biasing voltage slightly in excess of the threshold voltage of the transistors to the input lines.

Abstract: A memory array comprised of floating gate, direct write nonvolatile memory cells having cell interiors which are interconnected by successive adjacent rows to share column lines between adjacent columns of cell and thereby reduce the column line pitch.

Abstract: The circuit and structure of a direct write differential nonvolatile memory cell. The features of the cell include high speed read sensing, write without a prior erase operation, single polysilicon fabrication capability, and memory margining capabilities. The structural and functional symmetry maximizes cell density while providing complementary differential operation. In a preferred arrangement, the cell utilizes a pair of cross-coupled, capacitively complementary, centrally disposed floating gate electrodes. The cell is written directly by the provision of complementary signals on a pair of program lines, which lines are capacitively coupled to the floating gate electrodes. The data state of the cell is sensed by conduction in two bit lines, the conductive states of the lines being determined by the charge transferred onto the two floating gate electrodes during the simultaneous but complementary programming of such electrodes.

Abstract: A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct write mode, and characterized by its absence of read disturb. In one form of its practice, the floating gate is divided into three regions situated with relation to specified regions in the substrate. The first region of the floating gate is dielectrically isolated from a conductively doped region in the substrate so as to form a capacitor; the second region is similarly situated, but forms a significantly smaller capacitor and utilizes a dielectric suitable for Fowler-Nordheim tunneling or Poole-Frenkel conduction of charge therethrough; and the third region overlaps a channel of a field effect type sense transistor, conduction through which is responsive to the charge resident on the floating gate.

Abstract: An EEPROM cell which is programmed to a 1 or .0. binary state regardless of the prior state of the cell, that is, without erasing. The cell construction includes silicon nitride capacitors between the floating gate and the programming electrodes which enhances the programming characteristics and the endurance and permits the use of a relatively simple double layer polysilicon process and semiconductor structure.

Abstract: A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed.

Abstract: A process for forming zener diodes from an IC structure having coextensive layers of gate silicon dioxide and polycrystalline silicon on a substrate and self-aligned with a diffused region in the substrate. A differential oxidation of the polycrystalline silicon and substrate silicon is followed in turn by a silicon dioxide etch to expose only the polycrystalline silicon layer. Thereafter, the exposed polycrystalline silicon is etched with an etchant that does not materially etch silicon dioxide. The exposed substrate is then subjected to an ion implantation, performed with an energy sufficient to locate the peak impurity concentration below the substrate surface, and a dose sufficient to moderately dope the area originally under the polycrystalline silicon electrode while reducing the effective concentration of the opposite impurity type dopant in the diffused region of the substrate.

Abstract: A process for fabricating an electrical contact which connects an epitaxial layer, well, or substrate with a metallic interconnect layer during the course of creating active integrated circuit devices in a semiconductor wafer. The process forms self-aligned contacts by establishing the contact locations coincident with the definition of the active regions, at an early step in the wafer fabrication process. Thereafter, a gate silicon dioxide layer and a polycrystalline silicon electrode layer are combined to mask the contact region surface from intermediate process environments, e.g., ion implantation and POCl.sub.3 diffusion operations. As the wafer fabrication process approaches conclusion, the contact region is opened by a selective etch of the polycrystalline silicon and the silicon dioxide layers, an enhancement implant into the surface of the contact region, a hydrogen environment annealing operation, and a deposition and patterning of the metallic interconnect layer.