Abstract: A method for determining the thermal history of an object is disclosed. The object carries at least two thermal calibration materials having different activation energies. The method comprises: first, exposing an object to a thermal treatment; second, detecting the change in each of the calibration materials caused by the thermal treatment; and third, determining the thermal history of the thermal treatment from the detected changes.Also disclosed are thermal history recording devices comprising one or more metal insulator semiconductor (MIS) capacitors. The insulating layer is non-uniformly doped with mobile charged carriers. Two or more MIS capacitors, each having different activation energies, may be mounted in a common support structure to provide a thermal memory cell. The thermal cells may be used in conjunction with an apparatus for determining the thermal history of the cells as also dislcosed herein.

Abstract: A method for determining the thermal history of an object is disclosed. The object carries at least two thermal calibration materials having different activation energies. The method comprises: first, exposing an object to a thermal treatment; second, detecting the change in each of the calibration materials caused by the thermal treatment; and third, determining the thermal history of the thermal treatment from the detected changes.Also disclosed are thermal history recording devices comprising one or more metal insulator semiconductor (MIS) capacitors. The insulating layer is non-uniformly doped with mobile charged carriers. Two or more MIS capacitors, each having different activation energies, may be mounted in a common support structure to provide a thermal memory cell. The thermal cells may be used in conjunction with an apparatus for determining the thermal history of the cells as also disclosed herein.

Abstract: A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical PNP. The PNP emitter is formed with a Schottky contact such that only the PNP base region is contained in the NPN emitter junction structure. The structure uses a separately masked ion/implant for the NPN intrinsic base implant which also forms the PNP collector region so that the PNP base doping profile can intercept the PNP collector profile at a lower concentration resulting in lower collector/base capacitance, lower series collector resistance and higher collector/base breakdown voltage for the PNP. Since the base doping concentration is lower in the structure and the emitter has no sidewall capacitance, the PNP emitter-base capacitance is greatly reduced. These features result in an improved frequency response for the PNP structure.

Abstract: A double level metal interconnection structure and process for making same are disclosed, wherein an etch-stop layer is formed on the first metal layer to prevent over-etching thereof when forming the second level metal line in a via hole in an insulating layer thereover, by means of reactive plasma etching. The etch-stop layer is composed of chromium and the reactive plasma etching is carried out with a halocarbon gas.

Abstract: A double level metal interconnection structure and process for making same are disclosed, wherein an etch-stop layer is formed on the first metal layer to prevent over-etching thereof when forming the second level metal line in a via hole in an insulating layer thereover, by means of reactive plasma etching. The etch-stop layer is composed of chromium and the reactive plasma etching is carried out with a halocarbon gas.