Abstract: A redundant clock system (8) keeps active and standby clock signals in phase with one another through way of a pair of cross-connected phase corrector circuits (PC1 and PC2) each of which operate off one of a pair of frequency locked, asynchonous, master clocks, or a delay compensated signal from a delay connector circuit (103, 104) of the phase corrector (PC1 or PC2). With such a redundant system, a method of switchover is provided in which all clock bus interface circuits are caused to select a standby phase corrector circuit to be active and then causing the previously active phase corrector circuit to operate as the standby to reduce timing errors caused by phase discontinuity.