Abstract: A location system and a location system on a chip (LCoS) and method are described.

Abstract: A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified.

Abstract: The invention provides a color processing system comprising an image capture device for capturing a scene and providing first color image data representative of the scene. A color space transformer is coupled to the image capture device for transforming the first color image data to second color image data. A first display device is coupled to the color transformer. The first display device displays the scene as represented by the second color image data. The color transformer includes a processor programmed to perform a matrix operation upon the first color image data by selecting matrix elements from a look up table (LUT) comprising pre-computed values.

Abstract: A method and apparatus for synchronizing clocks using an early clock are described.

Abstract: A polarization control system includes a light source that generates two light beams with different polarization states and optical frequencies. A polarization state modulator changes the polarization states of the two light beams. A first detector path generates a first beat signal from the two light beams passing through a first polarizer. A second detector path generates a second beat signal from the two light beams passing through a second polarizer that is oriented substantially orthogonal to the first polarizer. An amplitude detector generates an amplitude beat signal from the first and the second beat signals. The system then uses the amplitude beat signal to determine how to adjust the polarization state modulator in order to generate the first and the second light beams with the desired polarization states.

Abstract: A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

Abstract: A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.

Abstract: A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively.

Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.

Abstract: An apparatus and method for dependency tracking and register file bypass controls using a scannable register file are provided. With the apparatus and method, a scannable register file array is provided and used to track the stage of any instruction in the execution unit. Every entry in the target vector is updated every cycle to stay synchronized with the instructions in the execution unit. To keep the register file array synchronized with the instructions in the execution unit, a right shift of all the data in each entry of the register file array occurs every cycle. The scan port of the register file array cells is used as the shift function.

Abstract: The invention provides a herbal cellulite treatment employing, in preferred embodiments, topical treatments, both method and cosmetic composition, wherein a refined lipophilic extract, and preferably also a refined aqueous extract of a Malvaceae plant, preferably whole Hibiscus Abelmoschus, are applied to the skin overlying cellulite-afflicted tissues. The treatments are intended to last at least four, and preferably eight or more weeks. Clinical tests show suprisingly superior results to those obtainable with aminophylline compositions. Inventive treatments can reduce thigh diameters and fatty layer thickness, as well as skin condition. In vitro tests show remarkable lipolytic properties, apparently attributable to .beta.-receptor stimulation, and valuable lipogenesis inhibition properties apparently attributable to .alpha..sub.2 -blocking. Preferred extracts show low toxicity.