Abstract: A CAM including a set of priority registers for storing information from one port and a set of non-priority registers for storing information from a second port. The CAM also includes a memory array that is coupled to both sets of registers. A port arbiter within the CAM determines which set of registers is given access to the memory array. Also described is a method for controlling access to the memory array. A lock interval is indicated before the priority registers initiate access to the memory array. During the lock interval, access to the memory by the non-priority registers is delayed if the access cannot be completed before the priority registers begin access.