Patents by Inventor Rayshan Visvanathan

Rayshan Visvanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication of corrugated gate dielectric structures using atomic layer etching
    Patent number: 11417849
    Abstract: Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 16, 2022
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Rayshan Visvanathan, Diana Torres Sanchez, Gregory L. Whiting
  • Fabrication Of Corrugated Gate Dielectric Structures Using Atomic Layer Etching
    Publication number: 20200381641
    Abstract: Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 3, 2020
    Inventors: Rayshan Visvanathan, Diana Torres Sanchez, Gregory L. Whiting