Abstract: A semiconductor photomultiplier module (20; 30; 40) comprises a first semiconductor chip (21; 31; 41) disposed in a first plane and comprising an array (21.1) of single-photon avalanche diodes (SPAD), a second semiconductor chip (22; 32; 42) disposed in a second plane and comprising a first part of an electronic read-out circuit, and a third semiconductor chip (26; 36; 46) comprising a second part of the electronic read-out circuit, wherein the first semiconductor chip (21; 31; 41) and the second semiconductor chip (22; 32; 42) are arranged in a stacked relationship and vertical electrical interconnects (23) are arranged to electrically interconnect the first semiconductor chip (21; 31; 41) with the second semiconductor chip (22; 32; 42).

Abstract: A mirror includes a carrier, a reflecting layer disposed above a main face of the carrier, and a transparent layer disposed above the reflective layer. The carrier includes a base body, and the base body includes one or more of a material comprising a density in a range from 0.1 to 1.0 g/cm3, a porous material, a foamed material, a material comprising a structure containing closed cells, a material comprising a honeycomb structure, or a structure containing carbon fibers.

Abstract: A mirror includes a carrier, a reflecting layer disposed above a main face of the carrier, and a transparent layer disposed above the reflective layer. The carrier includes a base body, and the base body includes one or more of a material comprising a density in a range from 0.1 to 1.0 g/cm3, a porous material, a foamed material, a material comprising a structure containing closed cells, a material comprising a honeycomb structure, or a structure containing carbon fibers.

Abstract: The silicon-based photomultiplier device comprises a substrate (1), a first layer (2) of a first conductivity type, a second layer (3) of a second conductivity type formed on the first layer, wherein the first layer (2) and the second layer (3) form a p-n junction, wherein the first layer (2) and the second layer (3) are disposed on or above the substrate (1). A material layer (15) between the substrate (1) and the first layer (2) fulfills the function of a light absorber, thereby efficiently suppressing crosstalk between adjacent cells of the device. Material layer (15) may further serve as an electrode for readout of electrical signals from the device.

Abstract: The silicon-based photomultiplier device comprises a substrate (1), a first layer (2) of a first conductivity type, a second layer (3) of a second conductivity type formed on the first layer, wherein the first layer (2) and the second layer (3) form a p-n junction, wherein the first layer (2) and the second layer (3) are disposed on or above the substrate (1). A material layer (15) between the substrate (1) and the first layer (2) fulfils the function of a light absorber, thereby efficiently suppressing crosstalk between adjacent cells of the device. Material layer (15) may further serve as an electrode for readout of electrical signals from the device.

Abstract: A cell for a silicon based photoelectric multiplier may comprise a substrate of a second conductivity type, a first layer of a first conductivity type, and/or a second layer of the second conductivity type formed on the first layer. The first layer and the second layer may form a first p-n junction, and the substrate may be configured such that in operation of the photoelectric multiplier from a quantity of light propagating towards a back side or side walls of the photoelectric multiplier, a negligible portion returns to a front side of the photoelectric multiplier.

Abstract: The present disclosure relates to photodetectors with high efficiency of light detection, and may be used in a wide field of applications, which employ the detection of very weak and fast optical signals, such as industrial and medical tomography, life science, nuclear, particle, and/or astroparticle physics etc. A highly efficient CMOS-technology compatible Silicon Photoelectric Multiplier may comprise a substrate and a buried layer applied within the substrate. The multiplier may comprise cells with silicon strip-like quenching resistors, made by CMOS-technology, located on top of the substrate and under an insulating layer for respective cells, and separating elements may be disposed between the cells.

Abstract: A cell for a silicon based photoelectric multiplier may comprise a substrate of a second conductivity type, a first layer of a first conductivity type, and/or a second layer of the second conductivity type formed on the first layer. The first layer and the second layer may form a first p-n junction, and the substrate may be configured such that in operation of the photoelectric multiplier from a quantity of light propagating towards a back side or side walls of the photoelectric multiplier, a negligible portion returns to a front side of the photoelectric multiplier.

Abstract: The present disclosure relates to photodetectors with high efficiency of light detection, and may be used in a wide field of applications, which employ the detection of very weak and fast optical signals, such as industrial and medical tomography, life science, nuclear, particle, and/or astroparticle physics etc. A highly efficient CMOS-technology compatible Silicon Photoelectric Multiplier may comprise a substrate and a buried layer applied within the substrate. The multiplier may comprise cells with silicon strip-like quenching resistors, made by CMOS-technology, located on top of the substrate and under an insulating layer for respective cells, and separating elements may be disposed between the cells.

Abstract: The invention relates to high-efficient light-recording detectors and can be used for nuclear and laser engineering, and in technical and medical tomography etc. The inventive silicon photoelectric multiplier (variant 1) comprising a p++ type conductivity substrate whose dope additive concentration ranges from 1018 to 1020 cm ?3 and which consists of cells, each of which comprises a p? type conductivity epitaxial layer whose dope additive concentration is gradually changeable from 1018 to 1014 cm?3 and which is grown on the substrate, a p? type conductivity layer whose dope additive concentration ranges from 1015 to 1017 cm?3 and a n+ type conductivity layer whose dope additive concentration ranges from 1018 to 1020 cm?3, wherein a polysilicon resistor connecting the n+ type conductivity layer with a feed bar is arranged in each cell on a silicon oxide layer and separating elements are disposed between the cells.

Abstract: The invention relates to high-efficient light-recording detectors and can be used for nuclear and laser engineering, and in technical and medical tomography etc. The inventive silicon photoelectric multiplier (variant 1) comprising a p++ type conductivity substrate whose dope additive concentration ranges from 1018 to 1020 cm?3 and which consists of cells, each of which comprises a p-type conductivity epitaxial layer whose dope additive concentration is gradually changeable from 1018 to 1014 cm?3 and which is grown on the substrate, a p-type conductivity layer whose dope additive concentration ranges from 1015 to 1017 cm?3 and a n+ type conductivity layer whose dope additive concentration ranges from 1018 to 1020 cm?3, wherein a polysilicon resistor connecting the n+ type conductivity layer with a feed bar is arranged in each cell on a silicon oxide layer and separating elements are disposed between the cells.