Patents by Inventor Re-Long Chiu

Re-Long Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11175257
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 16, 2021
    Assignee: WaferTech, LLC
    Inventors: Re-Long Chiu, Jason Higgins
  • Publication number: 20180299402
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Application
    Filed: June 22, 2018
    Publication date: October 18, 2018
    Inventors: Re-Long CHIU, Jason HIGGINS
  • Patent number: 10067084
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 4, 2018
    Assignee: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Jason Higgins
  • Patent number: 9362443
    Abstract: A solar cell with an absorber layer including three dimensional tubular projections and the method for forming the same, is provided. The three dimensional tubular projections are formed in various configurations and include surfaces facing in various directions and are adapted to absorb sunlight directed to the solar cell panel at various angles. The method for forming the absorber layer includes introducing impurities onto a layer over a solar cell substrate to form as nucleation sites and depositing an absorber layer to form a base layer portion and tubular projections at the nucleation sites. The solar cell is exposed to sunlight and the absorber layer including the three dimensional tubular projections, absorbs direct and reflected sunlight directed to the solar cell at various angles.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 7, 2016
    Assignee: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying
  • Patent number: 9261341
    Abstract: An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 16, 2016
    Assignee: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Sharon Ying
  • Patent number: 9136271
    Abstract: A one-time programmable (OTP) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 15, 2015
    Assignee: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying, Wen-Szu Chung
  • Publication number: 20150236136
    Abstract: Provided are stacked gate floating gate transistors and split gate floating gate transistors having floating gates with respective upper surfaces that include upwardly extending pillars which are sharp, densely packed apices in some embodiments, and an increased surface area. The increased surface area enables lower erase voltages to be used and enables smaller device feature sizes, particularly for split gate floating gate transistors. A method for forming the floating gate is also provided, and includes using a polymeric or other sacrificial layer over a polysilicon layer, etching to remove most of the polymeric or other sacrificial layer but leaving residual specks on the polysilicon layer, the specks having sizes in the nanometer range. The residual specks serve as masking objects in a subsequent operation that forms the associated pillars by partially etching the polysilicon layer.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: WaferTech, LLC
    Inventors: Re-Long CHIU, Arthur CHIN, Yun CHONG, Delilah BERNABE
  • Publication number: 20150192539
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Re-Long Chiu, Jason Higgins
  • Patent number: 9000783
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 7, 2015
    Assignee: Wafertech, LLC
    Inventors: Re-Long Chiu, Jason Higgins
  • Publication number: 20150007739
    Abstract: An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 8, 2015
    Inventors: Re-Long CHIU, Sharon YING
  • Publication number: 20140261655
    Abstract: A solar cell with an absorber layer including three dimensional tubular projections and the method for forming the same, is provided. The three dimensional tubular projections are formed in various configurations and include surfaces facing in various directions and are adapted to absorb sunlight directed to the solar cell panel at various angles. The method for forming the absorber layer includes introducing impurities onto a layer over a solar cell substrate to form as nucleation sites and depositing an absorber layer to form a base layer portion and tubular projections at the nucleation sites. The solar cell is exposed to sunlight and the absorber layer including the three dimensional tubular projections, absorbs direct and reflected sunlight directed to the solar cell at various angles.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying
  • Publication number: 20140233319
    Abstract: A one-time programmable (OTP) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: WaferTech, LLC
    Inventors: Re-Long CHIU, Shu-Lan YING, Wen-Szu CHUNG
  • Patent number: 8794151
    Abstract: An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: August 5, 2014
    Assignee: Wafertech, LLC
    Inventors: Re-Long Chiu, Sharon Ying
  • Patent number: 8743585
    Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 3, 2014
    Assignee: Wafertech, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying, Wen-Szu Chung
  • Publication number: 20130301356
    Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Application
    Filed: July 12, 2013
    Publication date: November 14, 2013
    Inventors: Re-Long CHIU, Shu-Lan Ying, Wen-Szu Chung
  • Patent number: 8508971
    Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: August 13, 2013
    Assignee: Wafertech, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying, Wen-Szu Chung
  • Publication number: 20130114343
    Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying, Wen-Szu Chung
  • Publication number: 20120132096
    Abstract: An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 31, 2012
    Applicant: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Sharon Ying
  • Publication number: 20120025853
    Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 2, 2012
    Applicant: WAFERTECH, LLC
    Inventors: Re-Long Chiu, Jason Higgins