Abstract: An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.

Abstract: A flip-chip circuit arrangement having improved thermal management includes a base substrate having a top surface which includes one or more bond pads thereon. The arrangement further includes a semiconductor substrate having circuitry and one or more bond pads thereon, wherein the one or more bond pads on the semiconductor substrate correspond to the one or more bond pads on the base substrate. The semiconductor substrate has one or more channels which extend from a top surface to a bottom surface thereof and the channels facilitate a transfer of heat due to power dissipation of the circuitry away from the semiconductor substrate.

Abstract: A method of forming a test configuration for an integrated circuit employing a controlled, collapse chip connection technology to attach to another substrate is disclosed. The method includes the steps of forming one or more vias in a semiconductor substrate corresponding to the integrated circuit and forming circuitry on a top surface of the semiconductor substrate. The method further includes filling the one or more vias with a conductive material to form conductive channels through the semiconductor substrate which selectively couples to the circuitry to provide control signals thereto and receive output signals therefrom. One or more bond pads are formed on a bottom surface of the semiconductor substrate and correspond to the one or more conductive channels.

Abstract: A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.

Abstract: A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.