Patents by Inventor Rebecca A. Jessep

Rebecca A. Jessep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7271349
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 7168164
    Abstract: Methods to shield conductive layer from via. A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 7061116
    Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
  • Patent number: 7061095
    Abstract: A printed circuit board and a system and method of embedding conductor channels into a printed circuit board. These conductor channels are used to provided increased power to circuits on the printed circuit board, provide shielding for these circuits and provide communications for these circuits. These conductor channels are created by ablating dielectric layers in the printed circuit board and depositing a conductive material therein.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Rebecca Jessep, Carolyn McCormick, Daryl Sato
  • Patent number: 6941537
    Abstract: A standoff device provides predetermined control of a standoff distance between electrical components mounted together with opposing conductive grid array patterns. In an embodiment, a predetermined electrical function is provided by the device to at least one of the electrical components. The standoff device comprises a plurality of rigid one-piece standoff pins which, in an embodiment, contains one or more stops which buttress against the electrical components to serve as a distancing control structure. In an embodiment, the standoff device is integral with one of the electrical components.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 6, 2005
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato
  • Publication number: 20040238216
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Application
    Filed: July 8, 2004
    Publication date: December 2, 2004
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 6667090
    Abstract: A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Rebecca A. Jessep, Carolyn McCormick, Daryl A. Sato, John H. Dungan
  • Publication number: 20030145460
    Abstract: Standoff arrangements to control distance and provide electrical function.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato
  • Patent number: 6580174
    Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads, the one or more vents connecting an outer diameter of at least one of the one or more via in pads to a diameter larger than the via.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: June 17, 2003
    Assignee: Intel Corporation
    Inventors: Carolyn R. McCormick, Rebecca A. Jessep, John H. Dungan, David W. Boggs, Daryl A. Sato
  • Publication number: 20030091730
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Application
    Filed: September 4, 2002
    Publication date: May 15, 2003
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Publication number: 20030064546
    Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Carolyn R. McCormick, Rebecca A. Jessep, John H. Dungan, David W. Boggs, Daryl A. Sato
  • Publication number: 20030061590
    Abstract: A system and method of embedding conductor channels into a printed circuit board. These conductor channels are used to provided increase power to circuits on the printed circuit board, provide shielding for these circuits and provide communications for these circuits. These conductor channels are created by ablating dielectric layers in the printed circuit board and depositing a conductive material therein.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Inventors: David W. Boggs, Rebecca Jessep, Carolyn McCormick, Daryl Sato
  • Publication number: 20030057974
    Abstract: An arrangement of vias for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard vias, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Inventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
  • Publication number: 20030056365
    Abstract: A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Inventors: David W. Boggs, Rebecca A. Jessep, Carolyn McCormick, Daryl A. Sato, John H. Dungan
  • Publication number: 20030047348
    Abstract: Grid array mounting arrangements, including apparatus (sub-arrays, arrays, electronic components, systems) and methods.
    Type: Application
    Filed: September 10, 2001
    Publication date: March 13, 2003
    Inventors: Rebecca Jessep, Ray Askew, Daryl Sato, Jeff Krieger, Phil Geng