Patents by Inventor Rebecca G. Cole

Rebecca G. Cole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6713381
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Motorola, Inc.
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Patent number: 6429531
    Abstract: An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: August 6, 2002
    Assignee: Motorola, Inc.
    Inventors: Addi B. Mistry, Rina Chowdhury, Scott K. Pozder, Deborah A. Hagen, Rebecca G. Cole, Kartik Ananthanarayanan, George F. Carney
  • Publication number: 20020093098
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: January 18, 2002
    Publication date: July 18, 2002
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Publication number: 20020000665
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: April 5, 1999
    Publication date: January 3, 2002
    Inventors: ALEXANDER L. BARR, SURESH VENKATESAN, DAVID B. CLEGG, REBECCA G. COLE, OLUBUNMI ADETUTU, STUART E. GREER, BRIAN G. ANTHONY, RAMNATH VENKATRAMAN, GREGOR BRAECKELMANN, DOUGLAS M. REBER, STEPHEN R. CROWN