Abstract: A method of wireless communication at UE is disclosed herein. The method includes transmitting at least one of a first indication including UE capability information indicating that the UE is capable of transmitting in UL during one or more MGs or a second indication including information indicating a first set of slots corresponding to the one or more MGs. The method includes obtaining a configuration to transmit a set of UL transmissions based on at least one of the first indication or the second indication. The method includes transmitting, based on the configuration, the set of UL transmissions in the first set of slots corresponding to the one or more MGs.

Abstract: Compositions having pesticidal activity and methods for their use are provided. Compositions include isolated and recombinant polypeptide sequences having pesticidal activity, recombinant and synthetic nucleic acid molecules encoding the pesticidal polypeptides, DNA constructs comprising the nucleic acid molecules, vectors comprising the nucleic acid molecules, host cells comprising the vectors, and antibodies to the pesticidal polypeptides. Nucleotide sequences encoding the polypeptides provided herein can be used in DNA constructs or expression cassettes for transformation and expression in organisms of interest. The compositions and methods provided herein are useful for the production of organisms with enhanced pest resistance or tolerance. Transgenic plants and seeds comprising a nucleotide sequence that encodes a pesticidal protein of the invention are also provided. Methods are provided for producing the polypeptides disclosed herein, and for using those polypeptides for controlling a pest.

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

Abstract: A brachytherapy applicator is formed to use when administering therapeutic radiation to a particular patient's targeted area via brachytherapy. This process accesses image information for a patient that includes the targeted area and at least some adjacent non-targeted area. A control circuit uses that image information with prescribed dosing information for that patient to automatically generate a brachytherapy applicator design specifically to treat the particular patient's targeted area via brachytherapy. A corresponding brachytherapy applicator is then manufactured as a function, at least in part, of the brachytherapy applicator design to provide a manufactured brachytherapy applicator.

Abstract: Misconnected applicators are eliminated in a brachytherapy treatment system by associating the output channels of an afterloader with the channel numbers after the applicators have been coupled to the output channels. In addition, the brachytherapy treatment system ensures the delivery of a proper dose by identifying the exact locations of the distal ends of the applicators right before the radiation treatment is to begin, and determining the final dose based on the exact locations.

Abstract: A method and electronic device are provided. The electronic device includes a first dielectric layer; a metal patterned in the first dielectric layer; a second dielectric layer deposited on the first dielectric layer; and a metal via deposited in a channel in the second dielectric layer, the metal via being in contact with the patterned metal in the first dielectric layer. The channel is formed by removing at least a portion of a nanowall formed on the metal in the first dielectric layer.

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Abstract: Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: A current-voltage (IV) relationship of a pixel having a diode is initially determined. A first voltage is determined that does not cause the diode to emit light, and a first current across the diode is sensed by applying the first voltage. A predetermined current is determined based on the first voltage and the IV relationship. A ratio is determined based on the first current, a target current, and the predetermined current. A ratio voltage is determined by applying the ratio to a predetermined target voltage. If the first current is less than the predetermined current, then the ratio voltage is applied to supply a target current to the diode. If the first current is greater than the predetermined current, then a second voltage is determined by averaging the first test voltage and the ratio voltage, and the second voltage is applied to supply the target current to the diode.

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Abstract: Systems and methods are presently disclosed that compensate for temperature-based parasitic capacitance variation of a pixel of a display by causing a driver transistor of the pixel to enter an ohmic or linear region. A lookup table is generated based on temperatures at the pixel, diode voltages, and target diode currents or luminances at a diode of the pixel. A correction voltage is determined based on a target diode current or luminance, a temperature at the pixel, and the lookup table. A data voltage is applied corresponding to the target diode current or luminance and the correction voltage to the driver transistor.

Abstract: A brachytherapy applicator is formed to use when administering therapeutic radiation to a particular patient's targeted area via brachytherapy. This process accesses image information for a patient that includes the targeted area and at least some adjacent non-targeted area. A control circuit uses that image information with prescribed dosing information for that patient to automatically generate a brachytherapy applicator design specifically to treat the particular patient's targeted area via brachytherapy. A corresponding brachytherapy applicator is then manufactured as a function, at least in part, of the brachytherapy applicator design to provide a manufactured brachytherapy applicator.

Abstract: Systems and methods are presently disclosed that compensate for temperature-based parasitic capacitance variation of a pixel of a display by causing a driver transistor of the pixel to enter an ohmic or linear region. A lookup table is generated based on temperatures at the pixel, diode voltages, and target diode currents or luminances at a diode of the pixel. A correction voltage is determined based on a target diode current or luminance, a temperature at the pixel, and the lookup table. A data voltage is applied corresponding to the target diode current or luminance and the correction voltage to the driver transistor.

Abstract: A current-voltage (IV) relationship of a pixel having a diode is initially determined. A first voltage is determined that does not cause the diode to emit light, and a first current across the diode is sensed by applying the first voltage. A predetermined current is determined based on the first voltage and the IV relationship. A ratio is determined based on the first current, a target current, and the predetermined current. A ratio voltage is determined by applying the ratio to a predetermined target voltage. If the first current is less than the predetermined current, then the ratio voltage is applied to supply a target current to the diode. If the first current is greater than the predetermined current, then a second voltage is determined by averaging the first test voltage and the ratio voltage, and the second voltage is applied to supply the target current to the diode.