Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned in order to suppress oxide dielectric breakdown, using a shaped deep body junction that partly lies below the trench bottom to force voltage breakdown away from the trench surfaces and into the bulk of the semiconductor material, and using special procedures for growth of gate oxide at various trench corners.

Abstract: A process is disclosed for the etching of a tungsten layer on a semiconductor wafer through a photoresist mask to form a pattern of tungsten lines on the wafer. The process is characterized by a high selectivity to photoresist material and resistance to lateral etching or undercutting of the tungsten beneath the photoresist mask resulting in good profile control, i.e., low critical dimension loss in the etched tungsten pattern. The process comprises flowing SF.sub.6, N.sub.2, Cl.sub.2 gases into an etch chamber while maintaining a plasma in the chamber. In a preferred embodiment, the wafer in the etch chamber is immersed in a magnetic field during the etch to further enhance the selectivity of the etch to photoresist.