Abstract: A Direct Memory Access (DMA) Acceleration Device for substantially increasing a data transfer rate between a system memory and an Input/Output (I/O) device for use in a data processing system. The DMA Acceleration Device enables the system to subtantially double a data transfer rate between the system memory and the I/O device by generating necessary control and address signals. In a receive operation, the DMA Acceleration Device reads the data from the I/O device while the host processor simultaneously writes the previous data to the system memory. Similarly, in a transmit operation, the DMA Acceleration Device writes the data to the I/O device while the host processor simultaneously reads the subsequent data from the system memory. Transmit and Receive State Machines of the DMA Acceleration Device are programmed to control the sequencing of signals during the DMA mode, while being absolutely transparent to the system in a non-DMA mode of operation.

Abstract: An apparatus for injecting errors into a FDDI token ring network is disclosed. The error injection scheme operates by fooling a FORMAC into thinking it sent a real frame of data. This is done by using two RAM buffers. The RAM buffer normally accessed by the RBC/DPC becomes a SHADOW RAM during error injection operation. A dummy frame is loaded into the shadow RAM in order to fool the FORMAC. This data is just like the data that would be used if sending a normal frame, with the restriction that it must be shorter than the error injection data. The other buffer, the error injection RAM, contains the error injection frame. The error injection data is sent out to the media by switching a multiplexor. When the FORMAC is done transmitting the data, the multiplexor is switched back to the normal mode. Thus, the FORMAC is unaware of what happened and the token ring remains operational.