Abstract: Aspects of the present disclosure generally relate to wireless communications and, more particularly, to performing channel estimation with modifications for improved system performance. Aspects generally include receiving, at a user equipment (UE), reference signals from a base station in a current subframe, and performing channel estimation, wherein the channel estimation is based at least in part on the reference signals received in the current subframe, a mobility characteristic of the UE, and a configuration of subframes prior to the current subframe.

Abstract: Aspects of the present disclosure generally relate to wireless communications and, more particularly, to performing channel estimation with modifications for improved system performance. Aspects generally include receiving, at a user equipment (UE), reference signals from a base station in a current subframe, and performing channel estimation, wherein the channel estimation is based at least in part on the reference signals received in the current subframe, a mobility characteristic of the UE, and a configuration of subframes prior to the current subframe.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to transmission phenomena. The bit synchronizer includes a DC level estimator for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal. A delay module generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The timing signals correspond to early, on-time, and late sampling windows. The control module generates an output signal based on the timing signals such that the transmit and receive bit timing are synchronized. In one embodiment, the control module has an absolute value stage, an integration stage, and a signal selector. The signal selector is able to select between the timing signals, adjust the symbol rate to re-center the on-time gate, and memory swap to maintain correct averaging operations.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to received noise, signal fading, relative time drift, time jitter, and other transmission phenomena. The bit synchronizer (10) includes a DC level estimator (12) for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal. A delay module (14) generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The timing signals correspond to early, on-time, and late sampling windows. The control module (16) generates an output signal based on the timing signals such that the transmit and receive bit timing are synchronized. In one embodiment, the control module (16) has an absolute value stage (36), an integration stage (38), and a signal selector (40).