Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Abstract: An imaging cell and a method of forming the imaging cell are disclosed. The imaging cell includes a first transistor that has source, a drain, and a gate, and a second transistor that has a source, a drain, and a gate connected to the source of the first transistor. In addition, the cell has a photodiode that is partially formed over the source of the second transistor.

Abstract: The drain-to-source field leakage current and the device-to-device field leakage current that are caused by radiation-induced hole trapping in the field oxide region are reduced in the present invention by forming the source and drain regions a distance apart from the edge of the field oxide region.

Abstract: A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.

Abstract: In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.

Abstract: A method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device.

Abstract: Phosphorus-doped silicon oxide glass is flowed on an integrated circuit by raising the pressure in which that integrated circuit is placed above atmospheric for a selected period of time and heating said phosphosilicate glass to a selected temperature sufficient to cause said glass to flow at said pressure. The atmosphere in which the device is placed includes moisture to enhance the flow of the glass at temperatures substantially beneath those at which dopants in the underlying integrated circuit move. The result is that the electrical characteristics of the integrated circuit are not substantially altered during glass flow.